Abov MC97F6108A - Page 93

MC97F6108A User’s manual 10. Timer0/1/2/3
93
PWMxPRL (PWM0/1/2/3 Period Register Low, Write Case) : B6H, BEH, C6H, CEH
7
6
5
4
3
2
1
0
PWMxPRL7
PWMxPRL6
PWMxPRL5
PWMxPRL4
PWMxPRL3
PWMxPRL2
PWMxPRL1
PWMxPRL0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value: FF
H
PWMxPRL[7:0]
Tx PWM Period Low data
NOTE: Reading and writing is effective only when PWMxE = 1 and TxST = 0
TxDRH (Timer0/1/2/3 Data Register High, Write Case) : B7H, BFH, C7H, CFH
7
6
5
4
3
2
1
0
TxDRH7
TxDRH6
TxDRH5
TxDRH4
TxDRH3
TxDRH2
TxDRH1
TxDRH0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value: FF
H
TxDRH[7:0]
TxH Compare High data
NOTE: Be sure to clear PWMxE before loading this register.
PWMxPRH (PWM0/1/2/3 Period Register High, Write Case) : B7H, BFH, C7H, CFH
7
6
5
4
3
2
1
0
PWMxPRH7
PWMxPRH6
PWMxPRH5
PWMxPRH4
PWMxPRH3
PWMxPRH2
PWMxPRH1
PWMxPRH0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value: FF
H
PWMxPRH[7:0]
Tx PWM Period High data
NOTE: Reading and writing is effective only when PWMxE = 1 and TxST = 0
TMISR (Timer Interrupt Status Register) : D5H
7
6
5
4
3
2
1
0
-
-
-
-
TMIF3
TMIF2
TMIF1
TMIF0
-
-
-
-
R/W
R/W
R/W
R/W
Initial value: 0H
When TIMERx Interrupt occurs, this bit becomes ‘1’. This bit is cleared
automatically if TIMERx and global interrupt enable bit is set. For clearing bit, write
‘1’ to this bit.
TMIF3
0
No generation
1
generation
TMIF2
0
No generation
1
generation
TMIF1
0
No generation
1
generation
TMIF0
0
No generation
1
generation