GPIB OPERATION
3-2-40
THE STATUS BYTE
The Status Byte provides information about events and conditions within the instrument.
It may be read by a conventional Serial Poll or its value obtained as a response to the *STB?
query. Bits 0 to 5 and bit 7 are each single bit Summary Messages which may be of two types
(or not used at all).
(i) Query Status - a '1' indicates that an associated Queue is non-empty and has data
available to be read.
(ii) Status Register Summary - reports the occurrence of an enabled event monitored
by a Status Register Structure.
The Service Request Enable Register determines which of the bits can generate an SRQ,
this register may be set by *SRE or read by *SRE?. If the bitwise -AND of the Status Byte and
the Enable Register is non-zero the Flag Master Summary Status (<mss>) is True. Bit 6 of the
Status byte value read by *STB? holds <mss>. However bit 6 of the Status Byte when Serial
Polled is the Request For Service bit used to determine which device on the Bus has asserted
SRQ, and is cleared by a Serial Poll.
The IEEE 488.2 Standard defines bit 4 as Message Available (<mav>), the Queue
Summary for the Output Buffer, indicating whether any part of a Response Messages is available
to be read. Bit 5 is the Event Summary Bit (<esb>), the Summary Message from the Standard
Event Status Register.
In 2030 series, bit 7 is a Queue Summary for the Error Queue. Bits 1, 2, and 3 are Status
summaries for the Instrument Status, Coupling Status and Hardware Status Registers. Bit 0 is
unused.
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