FECFEC
Clock ConfigurationClock Configuration
TransceiverTransceiver
Multi lane mappingMulti lane mapping
Timing sourceTiming source
Select a source to synchronize all Ethernet transmitters to.
The possible sources are:
InternalInternal
ExternalExternal
GPSGPS
ReceivedReceived
IEEE 1588v2IEEE 1588v2
ReceivedReceived appears when the interface type is set to SFPSFP, SFP+SFP+, SFP28SFP28, QSFP+QSFP+,
QSFP28QSFP28, QSFP56QSFP56, QSFP-DDQSFP-DD or OSFPOSFP
IEEE 1588v2IEEE 1588v2 appears when the interface type is set to ElectricalElectrical SFPSFP, or SFP+SFP+.
Sync PortSync Port
This item appears when Interface Type is set to SFP28SFP28, QSFP28QSFP28, QSFP56QSFP56, or
OSFPOSFP. Selects the output of Sync Clock Output connector on MU104011A,
MU104014A, or MU104015A panel.
OffOff: does not output the clock.
1/81/8: outputs 1/8 divided clock of the data synchronized clock (approximately
3.222 GHz).
1/161/16: outputs 1/16 divided clock of the data synchronized clock (approximately
1.611 GHz).
Block Diagram of Tx Part (SFP28, QSFP28)
FEC enableFEC enable
This setting appears when Interface Type is set to SFP28SFP28, QSFP28QSFP28, QSFP56QSFP56,
QSFP-DDQSFP-DD, or OSFPOSFP.
When Interface Type is set to QSFP56QSFP56, QSFP-DDQSFP-DD, or OSFPOSFP, this setting is fixed
to OnOn.
OnOn: The calculated forward error correction data will be added to the 25G
Ethernet frame and the 100G Ethernet frame.
OffOff: FEC is not added to the 25G Ethernet frame and the 100G Ethernet frame.
Displays the Transceiver information.
In case of 40G or 100G interface, touching the Lane MappingLane Mapping button launches
the following dialog box.
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