Model 8640B TM 9-4935-601-14-7&P
SERVICE SHEET 21
PRINCIPLES OF OPERATION
General (A8A2)
The lock mode is entered as follows: Cross-coupled NAND gates U3A and U3B form an RS flip-flop. The
output of U3A is low in the count mode and goes high after S1 is depressed and TIME BASE goes low. It
remains high until S1 is unlocked. Transistor Q1 and diodes CR1 and CR2 form an OR gate, with TIME
BASE and S1 as inputs.
When the phase lock error exceeds a predetermined limit, an error condition exists and a low appears at
the input to NAND gate U16A and at the input to NAND gate U3D of the cross coupled pair formed by U3C
and U3D. The output of U3D goes high and turns on the Flash Oscillator (Service Sheet 20). The output of
U3C is normally high, but goes low when an error exists (with U3A high). The output of NAND gate U16C is
low when phase lock exists. This is true when the output of U3A is high (i.e., S1 has been depressed and
after that TIME BASE has gone low) and the output of U3C is high (i.e., in addition no error exists). The
output of U16C is delayed by the resistor-capacitor network of R38 and C7 and inverted by U4D which
enables the Stall Counter and the main counter. When an error occurs, the output of U16C goes high and
the counter reverts to the count mode until S1 has been released and then depressed. NAND gate U16D
prevents the error condition from reaching gate U3D when TP4 is grounded as an aid to troubleshooting.
Phase Lock Circuits (A8A2)
A phase error is sensed in the Null Phase Detector by detecting the difference in time of occurrence of the
999,999 count of the counter (see Service Sheet 20) and the TIME BASE signal. D flip-flops U26A and
U26B and NAND gate U15C form the phase detector. When phase locked, both set (S) inputs are high.
Between the low occurrences of COUNTER LOAD and TIME BASE, the Q outputs of both U26A and U26B
are low. If COUNTER LOAD goes high first, the Q output of U26B goes high first. When TIME BASE goes
high, the Q output of U26A goes high. Both inputs of NAND gate U15C are now high so the output goes
low, and after a slight delay through resistor-capacitor network R1 and C1 and OR gate U14C, both flip-
flops are cleared.
The Q output of U26B remained low longer than the Q output of U26A. If a high on TIME BASE had
occurred first, the opposite would have been true. If both occur simultaneously, both outputs remain high
for an equal duration. The Q output pulses of U26A and U26B are increased in duration by a pulse width
multiplier and then drive current sources which charge and discharge a storage capacitor. When the Q
output of U26B goes low it turns on transistor switch Q8. Capacitor C2 is at 10V when Q8 is off because
the inverting input of amplifier U29A is at 10V; the output of U29A is also at 10V since, with Q8 off, no
current flows through R7. When Q8 goes on, C2 rapidly discharges through Q8. The output of U29A goes
high to about 20V and remains at that voltage until Q8 switches off and C2 charges slowly to about 10OV.
Current source Q7 is on when the output of U29A goes high. In a similar manner amplifier U29B goes high
and turns on current source Q12 when the Q output of U26A goes low. Current source Q7 charges
capacitor C4 and Q12 discharges it. Any phase difference from the phase detector results in a net charge
or discharge (i.e., an increase or decrease in voltage) of C4. FET Q6 is a high impedance buffer amplifier
which drives buffer Q11. Q11 drives the Phase Lock Loop Filter in the FM shaping circuits (Service Sheet
2). In the EXPAND X10 mode transistors Q16 and Q17 are switched in. Resistor-capacitor networks R51
and C15, and R52 and C16 now hold Q16 and Q17 on longer which in turn hold transistors Q8 and Q9 on
longer to increase the duration of the pulse stretcher. Capacitor C17 is also switched in to reduce ripple on
C4. In the normal count mode U26A and U26B are both set and cleared, i.e., both Q and Q are high, the
current sources Q13 and Q14 are switched on to bias C4 at a nominal mid-range voltage.
Error Detector (A8A2)
If the phase lock tune voltage from Q11 is too high or too low, the limit of the lock range is approached so
an error exists. The error is sensed by transistors Q2 and Q15. The emitter of Q2 is held at 14.9V and Q15
normally holds Q2 on. If the base of Q15 is low, the collector current is insufficient to hold resistor R30 and
the base of Q2 at the 14.3V needed to keep Q2 on. If the base of Q15 is high, Q15 saturates and the
collector voltage rises as the base rises. When the collector voltage of Q15 exceeds 14.3V, Q2 switches
off and a low appears at the input of U16A which represents an error. Resistor-capacitor network R31 and
C6 filters the voltage to the base of Q2.
TROUBLESHOOTING
It is assumed that a problem has been isolated to the counter phase lock circuits as a result of using the
troubleshooting block diagrams. Troubleshoot by using the test equipment listed below, performing the
initial test conditions and control settings and following the procedures outlined in the table.
NOTE
If the counter phase lock circuits fail, the usual effect is that the generator
won't enter phase lock or that it won't break phase lock. Ensure that the
counter circuits shown on Service Sheet 20 operate correctly before checking
the phase lock circuits.
SERVICE SHEET 21 (Cont'd)
When the procedures in the table require that a point be grounded, they often depend upon multiple
groundings (ground probe or contact bounce) to work correctly. Clipping or touching a grounding
probe to a point will usually supply enough multiple groundings to make the procedure work.
The procedures in the table also depend upon the sequence of switch settings and groundings. If a
procedure does not work correctly, try ungrounding the test points, resetting the switches to the
Initial Control Settings, and repeating the procedures.
Test Equipment
Digital Voltmeter..................................................................................................... HP 3480B/3484A
Initial Test Conditions
Top cover removed (see Service Sheet F for removal procedure). A8 Counter/Lock Assembly
casting cover removed and A8A2 Counter/Lock Board Assembly removed and extended for service
(see Service Sheet B for procedure).
Initial Control Settings
COUNTER MODE: EXPAND ..........................................................Off
LOCK...............................................................Off
Source..................................................EXT 0 - 10
TIME BASE INT/EXT (on rear panel) ........................................................................INT
NOTE
If phase lock is broken when the TIME BASE VERN control is turned (with
COUNTER MODE set to INT, LOCK, and EXP X10), check Q16, Q17 and
associated circuitry. (This will probably happen when RANGE is set to 8 16
MHz).
Up/Down Counter and Display (A8A2, A8A4)
SERVICE SHEET 20
SERVICE SHEET 21 (Cont'd)
Counter Phase Lock Circuits Troubleshooting
Component or Circuit Test Conditions and Control Settings Normal Indication If Indication is Abnormal
COUNTER PHASE Initial conditions and settings.
LOCK CIRCUITS Perform the following steps in
(A8A2) sequence.
1. Ground TP4 to disable error
signal
2. Set COUNTER MODE
LOCK to ON
3. Set TIME BASE INT/EXT
to EXT (with no input - this
sets time base line high)
4. Connect DVM to TP6 (phase
lock tune line) and use a
grounding probe to momen-
tarily ground the following
points a. Check Q6, Q7, Q8,
a. Ground U14A pin 1 a. TP6 at any voltage from Q11, U26B, U29A, and
(clears U26) ≈+5 to +17V and stable associated circuitry
b. Ground U26B pin 11 (T) b. TP6 voltage should rise b. Same as above
within a few seconds to
≈+17V and U26B pin 8
(Q) should be low. U29A
pin 1 should be ≈+20V.
c. Ground U14A pin 1 c. TP6 voltage should re- c. Same as above
(clears U26) main at -+17V
d. Ground U26A pin 3 (T) d. TP6 voltage should de- d. Same as above
crease within a few
seconds to ≈+5V and
U26A pin 8 (Q) should
be low. U29B pin 7
should be -+20V.
e. Ground U14A pin 1 e. TP6 should remain at e. Same as above
(clears U26) ≈+5V
f. Set EXPAND to X10. f. Same results as steps a f. Check Q16, Q17, and
Repeat steps a through e through e associated circuitry
ERROR Initial conditions and settings. U3D pin 11 (error signal) Check Q2, Q15, U3, U16
DETECTOR Then set COUNTER MODE is ≈+5V (high) and associated circuitry
(A8A2) Source to INT and LOCK to
ON. Turn FREQUENCY
TUNE control cw.
Repeat above except turn Same as above Same as above
FREQUENCY TUNE control
ccw
Set COUNTER MODE U3D pin 11 (error signal) Same as above
LOCK to Off. Turn FRE- is ≈0Vdc (low)
QUENCY TUNE control.
LOCK EXPAND Initial conditions and settings. Gates and switches operate Check S1, Q1, U3, U4, U16,
SWITCHING Then set COUNTER MODE correctly and associated circuitry
(A8A2) Source to INT and exercise
EXPAND and LOCK
switches.
8-60
Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com
To Next Page
Loading...