273
7647H–AVR–03/12
Atmel ATmega16/32/64/M1/C1
In accordance with the Table 18-7, these 3 bits select the interrupt event which will generate the
update of the DAC input values. The update will be generated by the rising edge of the selected
interrupt flag whether the interrupt is enabled or not.
• Bit 2 – DALA: Digital to Analog Left Adjust
Set this bit to left adjust the DAC input data.
Clear it to right adjust the DAC input data.
The DALA bit affects the configuration of the DAC data registers. Changing this bit affects the
DAC output on the next DACH writing.
• Bit 1 – DAOE: Digital to Analog Output Enable bit
Set this bit to output the conversion result on D2A,
Clear it to use the DAC internally.
• Bit 0 – DAEN: Digital to Analog Enable bit
Set this bit to enable the DAC,
Clear it to disable the DAC.
21.4.2 Digital to Analog Converter input Register – DACH and DACL
When the DAC is used with a 10-bit output value, the value is written into the 16-bit register pair
DACH:DACL as two separate 8-bit writes. As such the DAC value should be written first the low
byte to DACL followed by the high byte value to DACH. Only when the DACH register is written
is the DAC value updated.
If you choose to use the DAC in left-adjust 8-bit mode then a single write to the DACH register
with the 8-bit value will suffice to update the DAC.
21.4.2.1 DALA = 0
Table 21-1. DAC Auto Trigger source selection
DATS2 DATS1 DATS0 Description
0 0 0 Analog comparator 0
0 0 1 Analog comparator 1
0 1 0 External Interrupt Request 0
0 1 1 Timer/Counter0 Compare Match
1 0 0 Timer/Counter0 Overflow
1 0 1 Timer/Counter1 Compare Match B
1 1 0 Timer/Counter1 Overflow
1 1 1 Timer/Counter1 Capture Event
Bit 76543210
- - - - - - DAC9 DAC8 DACH
DAC7 DAC6 DAC5 DAC4 DAC3 DAC2 DAC1 DAC0 DACL
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value00000000
00000000
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