GEFRAN-SIEI ARTDrive Vector V2 Series - Buffering the Regulator Supply

ARTDrive V2 series - Instruction Manual Chapter 4 Wiring Procedure • 69
4.9 Buffering the Regulator Supply
The power supply of the control section is provided by a switched mode power
supply unit (SMPS) from the DC Link circuit. The Drive is disabled as soon as
the voltage of the DC Link circuit is below the threshold value (U
Buff
). The regulator
supply is buffered by the energy of the DC Link circuit until the limit value (U
min
)
is reached. The buffer time is determined by the capacitance of the DC Link
capacitors. The minimum values are shown in the table below. The buffer time
(t
Buff
) can be extended by connecting external capacitors in parallel (on terminal
C and D).
Table 4.9.1: DC Link Buffer Time
Inverter
type
Internal
capacitance
Maximum
permissible external
capacitance
Maximum power
required by
switched mode
power supply
400Vac 460Vac 575Vac
Cstd [µF] [s] [s] [s] C
ext
[µF] P
SMPS
[W]
1007
220 0.165 0.25 0 65
1015
220 0.165 0.25 0 65
1022
330 0.24 0.37 0 65
1030
330 0.24 0.37 0 65
2040
830 0.62 0.95 0 65
2055
830 0.62 0.95 0 65
2075
830 0.62 0.95 0 65
3110
1500 1.12 1.72 1500 65
3150
1500 1.12 1.72 1500 65
4220
1800 1.54 2.3
4500 70
4300
2200 1.88 2.8
4500 70
4370
3300 2.83 4.2
4500 70
5450 4950 4.24 6.3 4500 70
5550 4950 4.24 6.3 4500 70
6750 6600 5.6 8.1 0 70
7900 6600 5.6 8.1 0 70
71100
9900 8.4 12.1
070
71320 14100 12.8 17.2 0 70
81600 14100 12.8 17.2 0 70
2002 157 0.31 0 65
2003 157 0.31 0 65
2005 313 0.62 0 65
3007 666 1.32 666 65
3010 666 1.32 666 65
3015 1000 1.97 1000 65
3020 1000 1.97 1000 65
4025
1100 2.02
1300 70
4030
1100 2.02
1300 70
4040
1566 2.87
1300 70
4050 2200 4.03 2500 70
5060 2200 4.03 2500 70
5075 3133 5.75 1500 70
avy4220
SMPS = Switched Mode Power Supply
Buffer time t
Buff
(minimum value) with
the internal capacitance at : AC Input
voltage =
AVy …-5 (575Vac)
AVy …-4 (230…480Vac)
Alternatively the control function “Power Loss Ridethru” may be used to provide
active buffering of the regulator supply by regeneration (see chapter 7,
FUNCTION / PLR THR menu).