Hioki 3332 - Page 115

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8.3 Interface Outline
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& & & & &
& & &
bit 2 bit 1
bit 0
ESB2 ESB1 ESB0
Logical sum
& & & & &
& & &
S
tatus byte register (STB)
Event status enable register 0 (ESER0)
Event status register 0 (ESR0)
bit 7 bit 6
bit 5
bit 4 bit 3 bit 2 bit 1 bit 0
DS FOR OT IE COR IDO PODI MODI
Event status enable register 1 (ESER1)
Event status register 1 (ESR1)
bit 7 bit 6
bit 5
bit 4 bit 3 bit 2 bit 1 bit 0
AOW AOA AOV OA OV HW HA HV
・・・ ・・・ ・・・ ・・・ ・・・ ・・・ ・・・
・・・ ・・・ ・・・ ・・・ ・・・ ・・・ ・・・
Logical sum
& & & & &
& & &
Event status enable register 2 (ESER2)
Event status register 2 (ESR2)
bit 7 bit 6
bit 5
bit 4 bit 3 bit 2 bit 1 bit 0
Unused
CODI CLO2 CIN2 CHI2 CLO1 CIN1 CHI1
・・・ ・・・ ・・・ ・・・ ・・・ ・・・ ・・・
Logical sum
bit 7 bit 6
bit 5
bit 4 bit 3 bit 2 bit 1 bit 0
DS FOR OT IE COR IDO PODI MODI
bit 7 bit 6
bit 5
bit 4 bit 3 bit 2 bit 1 bit 0
AOW AOA AOV OA OV HW HA HV
bit 7 bit 6
bit 5
bit 4 bit 3 bit 2 bit 1 bit 0
Unused
CODI CLO2 CIN2 CHI2 CLO1 CIN1 CHI1