Hioki 3332 - Page 116

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8.3 Interface Outline
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Event status register 0 (ESR0)
Event status enable register 0 (ESER0)
(Event register for unit and power integrated value: Set when the display has
been renewed.)
Bit 7
DS
Data Set
Sets at every time the measuring value is replaced.
Bit 6
FOR
Frequency Out
of Range
Sets when frequency becomes o.r.
Bit 5
OT
Output Time
Sets when achieved output time during integrating.
Sets when integrating has been started and stopped.
Not set when output time is 0000:00:00.
Bit 4
IE
Integrate End
Sets when integrating has been stopped.
Bit 3
COR
Comparator Out
of Range
Sets when the comparator value for either CH1 or 2
is outside the range (HI or LO). *1
Bit 2
IDO
Integrator Data
Over
Sets after sampling when power integrated value is
over (±999999M).
Bit 1
PODI
Plus Over Data
Integrate
Sets when the plus over data (o.r) is added to the
positive power integrated value.
Bit 0
MODI
Minus Over Data
Integrate
Sets when the minus over data (-o.r) is added to the
negative power integrated value.
Event status register 1 (ESR1)
Event status enable register 1 (ESER1)
(Event register for the measurement values: Set when the display has been
renewed.)
Bit 7
AOW
Average
Over-W
Input over data is included in average active power.
Bit 6
AOA
Average
Over-A
Input over data is included in average current value.
Bit 5
AOV
Average
Over-V
Input over data is included in average voltage value.
Bit 4
OA
OVER-A
Current input has peaked over (sets when OVER
lamp for current is lit).
Bit 3
OV
OVER-V
Current input has peaked over (sets when OVER
lamp for current is lit).
Bit 2
HW
HIGH-W
Active power input is out of range
Bit 1
HA
HIGH-A
Current input is out of range
Bit 0
HV
HIGH-V
Voltage input is out of range
Event status registers 0 to 2 are cleared in the following three situations:
① When a "
*
CLS" command is received.
② When an "ESR0?" query (for event status register 0), "ESR1?" query (for
event status register 1), or "ESR2?" query (for event status register 2) are
received.
③ When the unit is powered on.
*1:When the limit values of the comparator are both set to the same level,
bit 3 is set to 1 by a HI signal, and is unaffected by a LO signal.