HP Vectra User Manual

Transmit Buffer Register (XF8H)
This register contains the characters to be transmitted via the
serial connector. Data bit 0, the least significant bit (LSB), is
transmitted first and data bit 7, the most significant bit (MSB), is
the last bit transmitted.
Receive Buffer Register (XF8H)
This register contains the characters received via the serial
connector. Data bit
0, the least significant bit (LSB), is received
first and data bit
7, the most significant bit (MSB), is the last bit
received.
Bit 7
of the Line Control Register (XFBH) determines whether the
Transmit Buffer Register or the Divisor Latch Register LSB is
accessed, and whether the Interrupt Enable Register or the Divisor
Latch Register (MSB) is accessed.
Divisor latch Registers lSB and MSB (XF8H and
XF9H)
The divisor latch LSB (XF8H) and the divisor latch MSB (XF9H)
registers are
used to control the baud-rate of the transmitted and
received data.
The HP24540A
has a clock of 1.8432MHz. This frequency can be
divided by any divisor from 1
to 65,525 as set on the two divisor
latches. The output (baud out) frequency is 16 times the baud-
rate.
The
two divisor latches must be loaded to define the baud-rate
before attempting
to transmit or receive data. When either of the
latches
is loaded, a 16-bit baud-rate counter is immediately loaded
to prevent long counts on the first load.
Serial/Parallel Card 125

HP Vectra Specifications

General

Processor	Intel Pentium
RAM	Up to 128 MB
Storage	HDD (capacity varies by model)
Operating System	Windows 95
Graphics	Integrated
Ports	Serial, Parallel
Expansion Slots	ISA, PCI