Intel Arria 10 FPGA User Manual

Schematic Signal Name Pin Number I/O Standard Description
FPGA_CONFIG_D19 P9 1.8 V FPGA configuration data
FPGA_CONFIG_D20 M6 1.8 V FPGA configuration data
FPGA_CONFIG_D21 N9 1.8 V FPGA configuration data
FPGA_CONFIG_D22 R8 1.8 V FPGA configuration data
FPGA_CONFIG_D23 T8 1.8 V FPGA configuration data
FPGA_CONFIG_D24 P7 1.8 V FPGA configuration data
FPGA_CONFIG_D25 R7 1.8 V FPGA configuration data
FPGA_CONFIG_D26 R9 1.8 V FPGA configuration data
FPGA_CONFIG_D27 T9 1.8 V FPGA configuration data
FPGA_CONFIG_D28 T7 1.8 V FPGA configuration data
FPGA_CONFIG_D29 P8 1.8 V FPGA configuration data
FPGA_CONFIG_D30 R6 1.8 V FPGA configuration data
FPGA_CONFIG_D31 P6 1.8 V FPGA configuration data
FPGA_CVP_CONFDONE M14 1.8 V FPGA Configuration via
Protocol (CvP) done
FPGA_DCLK M9 1.8 V FPGA configuration clock
FPGA_NCONFIG E14 1.8 V FPGA configuration active
FPGA_NSTATUS J4 1.8 V FPGA configuration ready
FPGA_PR_DONE H12 1.8 V FPGA partial reconfiguration
done
FPGA_PR_ERROR K12 1.8 V FPGA partial reconfiguration
error
FPGA_PR_READY P12 1.8 V FPGA partial reconfiguration
ready
FPGA_PR_REQUEST T4 1.8 V FPGA partial reconfiguration
request
M5_JTAG_TCK P3 1.8 V JTAG chain clock
M5_JTAG_TDI L6 1.8 V JTAG chain data in
M5_JTAG_TDO M5 1.8 V JTAG chain data out
M5_JTAG_TMS N4 1.8 V JTAG chain mode
MAX5_BEN0 R10 1.8 V MAX V Byte Enable 0
MAX5_BEN1 M10 1.8 V MAX V Byte Enable 1
MAX5_BEN2 T12 1.8 V MAX V Byte Enable 2
MAX5_BEN3 P10 1.8 V MAX V Byte Enable 3
MAX5_CLK N11 1.8 V MAX V Clock
MAX5_CSN T11 1.8 V MAX V chip select
MAX5_OEN N10 1.8 V MAX V output enable
MAX5_WEN R11 1.8 V MAX V Write enable
continued...
6. Board Components
683526 | 2023.07.12
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Intel
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Arria
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10 FPGA Development Kit User Guide
63

Intel Arria 10 FPGA Specifications

General

Brand	Intel
Model	Arria 10 FPGA
Category	Microcontrollers
Language	English