Power Sub-system Intel
®
Entry Server Chassis SC5299-E TPS
Revision 3.1
Intel order number D37594-005
74
Item Description Loading Minimum Maximum Units
T
pwok_off
Delay from PWOK de-asserted to output voltags
(3.3V, 5V, 12V, -12V) dropping out of regulation
limits.
1
ms
T
pwok_low
Duration of PWOK being in the de-asserted state
during an off/on cycle using AC or the PSON signal.
100
ms
T
sb_vout
Delay from 5VSB being in regulation to O/Ps being in
regulation at AC turn on.
50 1000
ms
T
5VSB_holdup
Time the 5VSB output voltage stays within regulation
after loss of AC.
70
ms
Note:
T
vout_holdup
and T
pwok_holdup
are defined under 60% loading.
AC Input
Vout
PWOK
5VSB
PSON
T
sb_on_delay
T
AC_on_delay
T
pwok_on
T
vout_holdup
T
pwok_holdup
T
pson_on_delay
T
sb_on_delay
T
pwok_on
T
pwok_off
T
pwok_off
T
pson_pwok
T
pwok_low
T
sb_vout
AC turn on/off cycle
PSON turn on/off cycle
T
5VSB_holdup
Figure 16. Turn On/Off Timing (Power Supply Signals)
2.4.3.7 Residual Voltage Immunity in Standby Mode
Each DC/DC converter is immune to any residual voltage placed on its respective output
(typically a leakage voltage through the system from standby output) up to 500mV. There is no
additional heat generated, nor is there any stress of any internal components with this voltage
applied to any individual output, or all outputs simultaneously. It also does not trip the power
supply protection circuits during turn on.
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