Mitsubishi Electric MELSEC-Q/L - Page 1065

APPENDICES
Appendix 1 Operation Processing Time
1063
A
■Table of the time to be added when file register, extended data register, extended link register,
module access device, and link direct device are used
• When using L02SCPU, L02SCPU-P, L02CPU, L02CPU-P, L06CPU, L06CPU-P, L26CPU, L26CPU-P, L26CPU-BT, and
L26CPU-PBT
Device name Data Device specification
location
Addition time (s)
L02SCPU,
L02SCPU-P
L02CPU,
L02CPU-P
L06CPU,
L06CPU-P,
L26CPU,
L26CPU-P,
L26CPU-BT,
L26CPU-PBT
File register (R) When standard RAM is
used
Bit Source 0.100 0.100 0.048
Destination 0.220 0.220 0.038
Word Source 0.100 0.100 0.048
Destination 0.100 0.100 0.038
Double word Source 0.200 0.200 0.095
Destination 0.200 0.200 0.086
File register (ZR),
extended data
register (D),
extended link register
(W)
When standard RAM is
used
Bit Source 0.160 0.140 0.057
Destination 0.320 0.280 0.048
Word Source 0.160 0.140 0.057
Destination 0.160 0.140 0.048
Double word Source 0.260 0.240 0.105
Destination 0.260 0.240 0.095
Module access device (Un\G) Bit Source 15.000 11.700 11.200
Destination 21.300 15.400 15.300
Word Source 10.600 9.460 9.410
Destination 33.000 19.000 19.000
Double word Source 24.200 11.000 10.900
Destination 34.800 18.800 18.700
Link direct device (Jn\) Bit Source 70.900 41.600 37.900
Destination 120.100 63.200 58.100
Word Source 68.400 40.700 37.500
Destination 53.700 31.700 30.800
Double word Source 75.600 49.400 43.400
Destination 58.900 39.600 37.300