Mitsubishi Electric MELSEC-Q/L - 7-Segment Decode

7 APPLICATION INSTRUCTIONS
7.5 Data Processing Instructions
427
7
7-segment decode
SEG(P)
Processing details
• Decodes the data from 0 to F designated by the lower 4 bits of (S) to 7-segment display data, and stores at (D).
*1 Head number of bit device or lowest bit of word device
(S): Data to be decoded or head number of the devices where the data to be decoded is stored (BIN 16 bits)
(D): Head number of the devices where the decoding result will be stored (BIN 16 bits)
Setting
data
Internal device R, ZR J\ U\G Zn Constant
K, H
Others
Bit Word Bit Word
(S)  
(D)  
(S) Configuration of 7
Segments
(D) Display data
Hexadecimal Bit pattern B7 B6 B5 B4 B3 B2 B1 B0
*1
0 0000 00111111
1 0001 00000110
2 0010 01011011
3 0011 01001111
4 0100 01100110
5 0101 01101101
6 0110 01111101
7 0111 00100111
8 1000 01111111
9 1001 01101111
A 1010 01110111
B 1011 01111100
C 1100 00111001
D 1101 01011110
E 1110 01111001
F 1111 01110001
Basic
Process
High
performance
Redundant Universal LCPU
Command
Command
SEGP
SEG
S
S
SEG
SEGP
D
D
B0
B6
B3
B5
B1
B4 B
2