Mitsubishi Electric MELSEC-Q/L - Multiple CPU High-Speed Transmission Dedicated Instruction; Instructions for Multiple CPU High-Speed Transmission; Redundant System Instructions (for Redundant CPU); Instructions for Redundant System (for Redundant CPU)

2 INSTRUCTION TABLES
2.8 Multiple CPU High-speed Transmission Dedicated Instruction
79
2
2.8 Multiple CPU High-speed Transmission Dedicated
Instruction
Instructions for multiple CPU high-speed transmission
2.9 Redundant System Instructions (For Redundant
CPU)
Instructions for redundant system (for Redundant CPU)
Category Instruction
symbol
Symbol Processing details Execution
condition
Number
of basic
steps
Subset Reference
Writing
devices to
another
CPU
D.DDWR • In multiple CPU system, data
stored in a device specified by
host CPU ((S2)) or later is
stored by the number of write
points specified by ((S1)+1) into
a device specified by another
CPU (n) ((D1)) or later
10  Page 872
DP.DDWR 10 
Reading
devices
from
another
CPU
D.DDRD • In multiple CPU system, data
stored in a device specified by
another CPU (n) ((D1)) or later
is stored by the number of read
points specified by ((S1)+1) into
a device specified by host CPU
((S2)) or late
10  Page 876
DP.DDRD 10 
Category Instruction
symbol
Symbol Processing details Execution
condition
Number
of basic
steps
Subset Reference
System
switching
SP.CONTS
W
• Switches between the control
system and standby system at
the END processing of the scan
executed with the SP.CONTSW
instruction.
8  Page 880
D2D1S2S1D.DDWR n
D2D1S2S1 DP.DDWR n
D2D1S2S1D.DDRD n
D2D1S2S1 DP.DDRD n
SP.CONTSW SD