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Mitsubishi Electric MELSEC-Q/L - Writing to Host CPU Shared Memory

Mitsubishi Electric MELSEC-Q/L
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848
9 MULTIPLE CPU DEDICATED INSTRUCTIONS
9.1 Writing to the CPU Shared Memory of Host CPU
Writing to host CPU shared memory
S(P).TO
*1 Specified with the upper three digits of the four hexadecimal digits representing the start I/O number.
The value of n1 is specified by the upper three digits of the four hexadecimal digits representing the start I/O number of the
slot where the CPU module has been mounted.
Q00CPU, Q01CPU: The serial number (first five digits) is "04122" or later.
High Performance model QCPU: Function version B or later
n1: Start I/O number of the host CPU module
*1
(BIN 16 bits)
n2: CPU shared memory address of the write destination host CPU (BIN 16 bits)
Basic model QCPU: 0 to 511
High Performance model QCPU, Process CPU, Universal model QCPU: 0 to 4095
n3: Head number of the devices where data to be written is stored (BIN 16 bits)
n4: Number of data blocks to be written (BIN 16 bits)
Basic model QCPU: 1 to 320
High Performance model QCPU, Process CPU: 1 to 256
Universal model QCPU: 1 to 2048
(D): Device of the host CPU which is turned ON for one scan by the completion of writing (bits)
Setting
data
Internal device R, ZR J\ U\G Zn Constant
K, H
Others
Bit Word Bit Word
n1  
n2  
n3  
n4  
(D)  
Slot number Head I/O number n1
CPU slot 3E00 3E0
Slot 0 3E10 3E1
Slot 1 3E20 3E2
Slot 2 3E30 3E3
Redundant
LCPU
Basic
Process
High
performance
Universal
Ver. Ver.
Command
Command
n4
n4
n1
n1
n2
n2
S.TO
SP.TO
S.TO
SP.TO
n3
n3
D
D

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