Mitsubishi Electric MELSEC-Q/L - Page 851

9 MULTIPLE CPU DEDICATED INSTRUCTIONS
9.1 Writing to the CPU Shared Memory of Host CPU
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Processing details
• Writes device data of words n3 to n4 to the CPU shared memory address specified by n2 of the host CPU module or later
address. When writing is completed, the completion bit specified by (D) turns ON.
*2 Usable as a user free area when auto refresh setting is not made.
In addition, even when auto refresh setting is made, the auto refresh send range or later is usable as a user free area.
*3 Data cannot be written to the multiple CPU high speed transmission area of the Universal model QCPU with the S(P).TO instruction.
• When the number of write points is 0, no processing is performed and the completion device does not turn ON, either.
• The S.TO instruction can be executed once to one scan for each CPU. When execution condition is established at two or
more places at the same time, the S.TO instruction executed later is not processed since handshake is established
automatically.
• The number of data that can be written varies depending on the target CPU module.
Writing data to CPU shared memory can be performed using the intelligent function module device. For
intelligent function module device, refer to the User's Manual (Function Explanation, Program Fundamentals)
for the CPU module used.
• CPU shared memory address of the Basic model QCPU
• CPU shared memory address of the High Performance model QCPU, Process CPU and Universal model QCPU
*3
CPU module Number of write points
Basic model QCPU 1 to 320
High Performance model QCPU, Process CPU, 1 to 256
Universal model QCPU 1 to 2048
Device memory
Writes the
data of n4
words
Host CPU
n4
n3
CPU shared memory
of host CPU (n1)
n2
0(0H)
96(60H)
192(C0H)
511(1FFH)
CPU shared memory address
Host CPU operation information area
System area
Host CPU refresh area
*2
User free area
Write designation
prohibited area
Write designation
permitted area
0(0H)
512(200H)
2048(800H)
4095(0FFFH)
CPU shared memory address
Host CPU operation information area
System area
Host CPU refresh area
*2
User free area
Write designation
prohibited area
Write designation
permitted area