Mitsubishi Electric MELSEC-Q/L - Index

1071
I
INDEX
A
AnACPU and AnUCPU dedicated instructions
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1069
B
Basic model QCPU . . . . . . . . . . . . . . . . . . . . . . 14
Block switching method . . . . . . . . . . . . . . . . . . 127
Built-in Ethernet port LCPU . . . . . . . . . . . . . . . . 14
Built-in Ethernet port QCPU . . . . . . . . . . . . . . . . 14
C
Comparison of counters. . . . . . . . . . . . . . . . . 1067
Comparison of display instructions . . . . . . . . . 1068
Conditions for execution of instructions . . . . . . . 117
Configuration of Instructions. . . . . . . . . . . . . . . . 80
Counting step number . . . . . . . . . . . . . . . . . . . 118
CPU module. . . . . . . . . . . . . . . . . . . . . . . . . . . 14
D
Data that can be used by instructions . . . . . . . 1065
Designating data. . . . . . . . . . . . . . . . . . . . . . . . 81
Destination (D) . . . . . . . . . . . . . . . . . . . . . . . . . 80
Device range check. . . . . . . . . . . . . . . . . . . . . 111
G
GX Developer. . . . . . . . . . . . . . . . . . . . . . . . . . 14
GX Works2. . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
H
High Performance model QCPU . . . . . . . . . . . . . 14
High-speed Universal model QCPU . . . . . . . . . . 14
How to read instruction tables . . . . . . . . . . . . . . 23
I
I/O control mode . . . . . . . . . . . . . . . . . . . . . . 1065
Indexing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Indexing with 16-bit index registers . . . . . . . . . . . 92
Indexing with 32-bit index registers . . . . . . . . . . . 95
Indirect specification . . . . . . . . . . . . . . . . . . . . 105
Instructions whose designation format has been
changed
. . . . . . . . . . . . . . . . . . . . . . . . . . . . 1068
Intelligent function module device . . . . . . . . . . . . 14
L
L series . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
LCPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
List of association instructions . . . . . . . . . . . . . . 26
List of bit processing instructions . . . . . . . . . . . . 54
List of buffer memory access instructions . . . . . . 60
List of character string processing instructions . . . 62
List of clock instructions. . . . . . . . . . . . . . . . . . . 70
List of comparison operation instructions . . . . . . . 29
List of contact instructions . . . . . . . . . . . . . . . . . 25
List of data control instructions . . . . . . . . . . . . . . 68
List of data conversion instructions . . . . . . . . . . . .41
List of data processing instructions . . . . . . . . . . . .55
List of data table operation instructions . . . . . . . . .60
List of debugging and failure diagnosis instructions
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
List of dedicated instructions for Multiple CPU
high-speed transmission
. . . . . . . . . . . . . . . . . . .79
List of display instructions . . . . . . . . . . . . . . . . . .61
List of expansion clock instructions . . . . . . . . . . . .73
List of I/O refresh instructions. . . . . . . . . . . . . . . .46
List of instructions for network refresh . . . . . . . . . .77
List of instructions for reading from the CPU
shared memory of another CPU
. . . . . . . . . . . . . .78
List of instructions for reading/writing routing
information
. . . . . . . . . . . . . . . . . . . . . . . . . . . . .77
List of instructions for redundant system
(for Redundant CPU)
. . . . . . . . . . . . . . . . . . . . .79
List of instructions for writing to the CPU shared
memory of host CPU
. . . . . . . . . . . . . . . . . . . . . .78
List of logical operation instructions . . . . . . . . . . .48
List of other convenient instructions . . . . . . . . . . . 47
List of other instructions. . . . . . . . . . . . . . . . . 28,75
List of output instructions . . . . . . . . . . . . . . . . . . .27
List of program branch instructions . . . . . . . . . . . .46
List of program control instructions . . . . . . . . . . . .74
List of program execution control instructions. . . . . 46
List of rotation instructions . . . . . . . . . . . . . . . . . .51
List of shift instructions . . . . . . . . . . . . . . . . . 27,52
List of special function instructions . . . . . . . . . . . .65
List of structure creation instructions . . . . . . . . . . .58
List of switching instructions. . . . . . . . . . . . . . . . .69
List of termination instructions . . . . . . . . . . . . . . .28
M
MELSECNET(II, /B) . . . . . . . . . . . . . . . . . . . . . .14
MELSECNET/10 . . . . . . . . . . . . . . . . . . . . . . . .14
MELSECNET/H . . . . . . . . . . . . . . . . . . . . . . . . .14
N
Number of devices and number of transfers (n) . . .80
O
Operation processing time of Basic model QCPU
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .884
Operation processing time of High Performance
model QCPU/Process CPU/Redundant CPU
. . . .898
Operation processing time of LCPU . . . . . . . . .1025
Operation processing time of Universal model
QCPU
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .921
P
Process CPU . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Programming tool . . . . . . . . . . . . . . . . . . . . . . . .14
Q
Q series. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
QnCPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14