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Mitsubishi Electric MELSEC-Q/L - Matrix Input

Mitsubishi Electric MELSEC-Q/L
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6 BASIC INSTRUCTIONS
6.8 Other Convenient Instructions
353
6
Matrix input
MTR
Processing details
This instruction reads the input from 16 points n-rows starting from the input number designated by (S), then stores
fetched input data to area starting from the device designated by (D2).
One row (16 points) can be fetched in 1 scan.
Fetching from the first to the n th row is repeated.
The first through the 16th points store the first row of data and the next 16 points store the second row of data at the
devices following the device designated by (D2). For this reason, the space of 16 n points from the device designated by
(D2) are occupied by the MTR instruction.
(D1) is the output needed to select the row which will be fetched, and the system automatically turns it ON and OFF. It uses
the n points from the device designated by (D1).
Only device numbers divisible by 16 can be designated for (S), (D1) and (D2).
For n, a value in the range from 2 to 8 can be assigned.
No processing is performed in the following cases.
Operation error
In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0.
(S): Head input device (bits)
(D1): Head output device (bits)
(D2): Head number of the devices where matrix input data will be stored (bits)
n: Number of input rows (BIN 16 bit)
Setting
data
Internal device R, ZR J\ U\G Zn Constant
K, H
Others
Bit Word Bit Word
(S) (Only X)
(D1) (Only Y)
(D2) 
n 
The device number designated by (S), (D1), or (D2) is not divisible by 16.
The device designated by (S) is outside the actual input range.
The device designated by (D1) is outside the actual output range.
The space 16 n points following the device designated by (D2) exceeds the relevant device range.
The value for n is not between 2 and 8.
Error
code
Error details Q00J/
Q00/
Q01
QnH QnPH QnPRH QnU LCPU
4101 The device other than the input (X) was specified at (S).
The device other than the output (Y) was specified at (D1).

Basic
Redundant
Process
High
performance
Universal
LCPU
Command
MTR
n
S
MTR
D1
D2

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