Mitsubishi Electric MELSEC-Q/L - Writing to Host CPU Shared Memory

9 MULTIPLE CPU DEDICATED INSTRUCTIONS
9.1 Writing to the CPU Shared Memory of Host CPU
851
9
Writing to host CPU shared memory
TO(P), DTO(P)
*1 Specified with the upper three digits of the four hexadecimal digits representing the start I/O number.
*2 The setting range varies depending on the auto refresh setting range of the multiple CPU high speed transmission function.
The n1 is specified by the first 3 digits of the hexadecimal 4 digits which represent the head I/O number of the slot mounted to
the CPU module.
Processing details
■TO
• Writes device data of words (S) to n3 to the CPU shared memory address specified by n2 of the host CPU module or later
address.
• Q00CPU, Q01CPU: The serial number (first five digits) is "04122" or later.
n1: Start I/O number of the host CPU module
*1
(BIN 16 bits)
 Basic model QCPU: 3E0H
 Universal model QCPU: 3E0H to 3E3H
n2: CPU shared memory address of the write destination host CPU (BIN 16 bits)
 Basic model QCPU: 192 to 511
 Universal model QCPU: 2048 to 4095, 10000 to 24335
*2
(S): Data to be written or head number of the devices where the data to be written is stored (BIN 16 bits)
n3: Number of data blocks to be written (BIN 16 bits)
 Basic model QCPU: TO(P): 1 to 320, DTO(P): 1 to 160
 Universal model QCPU: TO(P): 1 to 14336, DTO(P): 1 to 7168
*2
Setting
data
Internal device R, ZR J\ U\G Zn Constant
K, H
Others
U
Bit Word Bit Word
n1  
n2  
(S)  
n3  
Slot number Head I/O number n1
CPU slot 3E00 3E0
Slot 0 3E10 3E1
Slot 1 3E20 3E2
Slot 2 3E30 3E3
High
performance
Process Redundant LCPU
Basic
Universal
Ver.
Command
Command
n3
n3
n1
n1
n2
n2
TO, DTO
TOP, DTOP
S
S
P
indicates an instruction symbol of TO/DTO.
Device memory
Writes the
data of n3
words
Host CPU
n3
CPU shared memory
of host CPU (n1)
n2
S