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2 INSTRUCTION TABLES
2.3 Sequence Instructions
*1 The number of steps may vary depending on the device being used.
*2 The number of steps may differ, depending on the device or CPU module to be used.
*3 For the High-speed Universal model QCPU, the number of basic steps is two.
Association instructions
*1 The number of steps may differ, depending on CPU modules.
Device Number of steps
Internal device, file register (R0 to R32767) 1
Direct access input (DX) 2
Devices other than above 3
CPU module Device Number of steps
Basic model QCPU
High Performance model QCPU
Process CPU
Redundant CPU
• Internal device, file register (R0 to R32767)
• Direct access input (DX)
1
Devices other than above 3
Universal model QCPU
LCPU
Internal device, file register (R0 to R32767) Number of basic steps
• Serial number access format file register (ZR), Extended data register
(D), Extended link register (W), Multiple CPU shared device
(U3En\G10000)
• Direct access input (DX)
Number of basic steps +1
Devices other than above Number of basic steps +2
Category Instruction
symbol
Symbol Processing details Execution
condition
Number
of basic
steps
Subset Reference
Connection ANB • AND between logical blocks
(Series connection between
logical blocks)
1 Page 138
ORB • OR between logical blocks
(Series connection between
logical blocks)
MPS • Memory storage of operation
results
1 Page 140
MRD • Read of operation results
stored with MPS instruction
MPP • Read and reset of operation
results stored with MPS
instruction
INV • Inversion of operation result 1 Page 143
MEP • Conversion of operation result
to rising edge pulse
1 Page 145
MEF • Conversion of operation result
to falling edge pulse
EGP • Conversion of operation result
to rising edge pulse (Stored at
Vn)
1 Page 146
EGF • Conversion of operation result
to falling edge pulse (Stored at
Vn)
*1
CPU module Number of basic steps
High Performance model QCPU
Process CPU
Redundant CPU
Universal model QCPU
LCPU
1
Basic model QCPU 2
ANB
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