Mitsubishi Electric MELSEC-Q/L - Multiplication and Division of Floating-Point Data (Double Precision)

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6 BASIC INSTRUCTIONS
6.2 Arithmetic Operation Instructions
Multiplication and division of floating-point data (double
precision)
ED*(P), ED/(P)
Processing details
■ED*
• Multiplies the 64-bit floating decimal point real number designated by (S1) by the 64-bit floating decimal point real number
designated by (S2) and stores the operation result at the device designated by (D).
• Values which can be designated at (S1), (S2) and (D) and which can be stored, are as follows:
0, 2
-1022
 | Designated value (stored value) | < 2
1024
• When the operation results in -0 or an underflow, the result is processed as 0.
• When an input value is set using a programming tool, a rounding error may occur. For precautions, refer to Page 89
Precautions.
■ED/
• Divides the 64-bit floating decimal point real number designated by (S1) by the 64-bit floating decimal point real number
designated by (S2) and stores the operation result at the device designated by (D).
• Values which can be designated at (S1), (S2) and (D) and which can be stored, are as follows:
0, 2
-1022
 | Designated value (stored value) | < 2
1024
• When the operation results in -0 or an underflow, the result is processed as 0.
• When an input value is set using a programming tool, a rounding error may occur. For precautions, refer to Page 89
Precautions.
(S1): Data to be multiplied/divided or head number of the devices where the data to be multiplied/divided is stored (real number)
(S2): Data for multiplying/dividing or head number of the devices where the data for multiplying/dividing is stored (real number)
(D): Head number of the devices where the operation result will be stored (real number)
Setting
data
Internal device R, ZR J\ U\G Zn Constant
E
Others
Bit Word Bit Word
(S1)   
(S2)   
(D)   
Universal LCPU
Basic
High
performance
Process Redundant
ED*, ED/
ED* P, ED/P
Command
Command
P
S1 S2
S1 S2
D
D
indicates an instruction symbol of ED*, ED/.
64-bit floating-point
real number
64-bit floating-point
real number
+3
64-bit floating-point
real number
D
+2
D
D
+1
D
+3 +2 +1 +3 +2 +1
S1 S1 S1 S1 S2 S2 S2 S2
64-bit floating-point
real number
64-bit floating-point
real number
+3
64-bit floating-point
real number
D
+2
D
D
+1
D
+3 +2 +1 +3 +2 +1
S1 S1 S1 S1 S2 S2
S2 S2