Mitsubishi Electric MELSEC-Q/L - Page 871

10 MULTIPLE CPU HIGH-SPEED TRANSMISSION DEDICATED INSTRUCTIONS
10.1 Overview
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• Program example when the multiple CPU high-speed transmission dedicated instruction is executed at CPU No.2
SM402
Turn-on for one
scan after RUN
MOV K1 SD796
Maximum number of
used blocks
(CPU No.1)
X20
Read instruction
SET M0
During execution the
DDRD instruction
U3E1\G10000.0 is turned on while CPU No.2 is executing the DP.DDRD instruction.
M0 U3E0\G10000.0 SM796
During execution
of the DDWR
instruction
CPU No.1 is
during execution
of the instruction
Number of used
blocks information
(CPU No.1)
SET G10000.0
U3E1\
CPU No.2 is during
execution of the
instruction
MOV K50 D1
Read instruction
DP.DDRD H3E0 D0 D1000 D1000 M1
Completion
status
Completion
device
RST M0
During execution of
the DDRD instruction
U3E1\G10000.0 is turned off at the completion of the DP.DDRD instruction.
RST G10000.0
U3E1\
CPU No.2 is during of
execution the instruction
M1
Completion device