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Mitsubishi Electric MELSEC-Q/L - Page 899

Mitsubishi Electric MELSEC-Q/L
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APPENDICES
Appendix 1 Operation Processing Time
897
A
*1 If the processing overlaps those of the other CPUs in a multiple CPU system, the processing time increases by a maximum of the
following time.
Table of the time to be added when file register, module access device or link direct device is
used
FROM Reading from
host CPU
shared
memory
n3=1 100 90
n3=320 440 420
Reading from
other CPU
shared
memory
n3=1 110 105
n3=320 305 290
TO Writing to host
CPU shared
memory
n3=1 100 95
n3=320 440 425
S.TO Writing to host
CPU shared
memory
n4=1 205 195
n4=320 545 525
For a system having only the main base unit
(Instruction processing time increase) = 4 0.54 (number of points processed) (number of other CPUs) (s)
For a system including extension base units
(Instruction processing time increase) = 4 1.30 (number of points processed) (number of other CPUs) (s)
Device name Data Device specification
location
Processing time (s)
Q00JCPU Q00CPU Q01CPU
File register (ZR) Bit Source 34 32
Destination 23 22
Word Source 13 12
Destination 98
Double word Source 14 13
Destination 10 9
Module access device (Un\G, U3En\G0
to G511)
BitSource 998277
Destination 167 137 129
Word Source 74 61 58
Destination 72 60 56
Double word Source 76 63 59
Destination 92 75 71
Link direct device (Jn\) Bit Source 178 147 137
Destination 303 248 233
Word Source 154 126 118
Destination 153 125 117
Double word Source 155 127 119
Destination 163 133 125
Instruction Condition (device) Processing time (s)
Q00JCPU Q00CPU Q01CPU

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