The
four
head
center taps are pulled
to
-10v
by resistors
R69, R72, R76,
and
R79
when the
associated head is not selected. When selected, the appropriate head center tap is pulled
positive
by
the corresponding head select switches (09, 010, 011, and 012).
During a Write operation,
+10v
is applied
to
the emitters
of
the head select switches via
01
when tracks 0 through
127
are selected. This voltage is decreased to approximately
+ 7.0v via
02
and resistor
R5
when tracks 128 through
202
are selected. The appropriate
selection is performed
as
follows: Write Mode (NLWMXG) and Erase Current Enable
(NLECEG) signals are inverted by U13-A and U18-E,
ORed by U15-D and fed to AND gates
U15-A and U15-B. The Demand Address Most
Significant Bit (128) signal (LDAMG) is fed
directly to U15-A and inverted
to
U15-B. The outputs of U15-A and U15-8 are fed via
open-collector drivers U11-A and U11-8
to
01 and
02.
This system ensures that write
current is appropriately reduced when writing on inner tracks where the flying height of the
head
is reduced.
During a
Read
operation, the head select switches are fed from approximately
Ov
via
03.
The
NOT (Write Mode or Erase Enable) signal from U18-F is used to drive the
open-collector driver U12-C which in turn is fed
to
the
em
itter
of
03.
5.4.2 WRITE AND ERASE DRIVERS
During a Write operation, the Write Mode (NLWMXG) signal Is inverted and, when true,
enables J-K flip-flop
U9
(zone F17). Inverters U13-F and U13-E provide
an
extra delay
which ensures that flip-flop
U9
is
always enabled in the reset state. Write Double
Frequency pulses (NLWDFT) are received and fed
to
the clock input of
U9.
These clock
pulses toggle the flip-flop for every pulse received as required by the double-frequency
code used.
The
0 and 0 outputs of
U9
are fed
to
two
identical pre-drivers
013
and 015. The outputs
of
013 and
015
drive the write drivers
014
and
016
whose emitters are returned to
approximately
-9v.
When
014
or
016
conduct, write current flows in one half of the
selected head. This current is defined by resistor
R65
or
R66
(as appropriate), the
-10v
supply, and the center tap voltage
(+
1
Ov
or +
7v
as
required). This yields typical write
currents of
35
ma peak for tracks 0 through 127 and 29
rna
for tracks 128 through
202.
The
base drive circuits of
all four transistors (013, 015, and 014, 016) have anti-saturation
diodes
CR13,
CR14,
CR15,
CR16, CR18, CR21,
CR19,
CR22
incorporated. Diodes
CR26
and
CR27
are used
to
isolate the head bus from the write Circuitry during a
Read
operation,
thus reducing noise injection.
CR23
and
CR24
prevent the inductive kickback of the
magnetic head windings from exceeding +
10v. Capacitors C8 and
C9
are speed up
capacitors which decrease write current rise time.
The
erase driver is separately enabled by the Erase Current Enable (NLECEG) Signal since
the erase current can
be
left on for a longer time than the write current. When NLECEG is
low.
017 (zone 016) is turned on via inverters U18-E and U11-E. This causes the base
of
018 to
be
switched
to
approximately
-4.3v
which enables the current source components
018
and
R59.
The
erase current is typically
40
ma, independent
of
the status
of
01
and
02.
The
return path for both write and erase drivers is via the emitter base junction of
Q19
through 022, and then to
-10v
via the
S10SS
line which is returned
to
-10v
through the
emergency unload relay.
022
is only enabled via 021 and
020
when the Power Clear Signal
(SPCSA)
is
at
a high (positive) level.
019
is used
as
a write current detector and is detailed
in
Paragraph 5.4.9.
5-15
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