PCC D3400 - Read Electronics

4.6.2.5 Current Monitor
The current monitor circuitry continuously checks the current outputs at a low logic level
to the write emergency circuitry during a write/erase operation. When both the Write Mode
and Erase Current Enable lines are at a high logic level, the write emergency circuitry
assumes that a
read operation is in progress and looks for a high logic level from the
current monitor.
Should the output of the current monitor be a low logic level at this time,
the write emergency monitor will sense
an illegal condition and cause the system to
perform an emergency unload.
In addition to the current monitoring function, the current monitor circuitry can disable the
flow of write or erase currents
to the read/write heads. The Power Clear signal (SPCSA)
generated on the Servo PCBA indicates the status of the regulated dc voltages and
controls a transistor switch in series with the common write/ erase current path.
In case of
a power failure,
SPCSA goes to a low level, causing the transistor switch to open the
write/ erase current line. This action prevents the writing of erroneous information on the
disk surface during a power failure emergency unload condition.
4.6.3 READ ELECTRONICS
A Read Enable (IREXR) signal from the system 110 interface conditions the Read/Write
circuitry
to perform a read operation. Certain readiness checks must be performed by the
disk drive Function
Control Logic circuitry before information can be transferred from the
surface of the disk to the system
I/O interface. The selected disk drive must be in the
Ready condition; this implies that the
following conditions exist:
(1) The heads are positioned over a legal track address.
(2) On Iy one head is selected.
(3) The Write Enable and Erase Current Enable lines are both high and the current
monitor senses no write or erase current flow.
The Read Electronics are activated when both the Write Mode and Erase Current Enable
inputs to the Read/Write
PCBA are at a high level. This condition is locally ANDed
resulting
in the Read/Write head windings being connected to the read preamplifier. The
amplifier
read data are filtered, peak detected, digitized, and decoded before being
suitable for
transmiSSion to the using system interface. When the Read Enable Control
(NLRECG) signal to the Read/Write
PCBA goes low, the Read Data (lRDXR) and Read
Clocks (IRCXD) are gated onto the system I/O interface I ines. A detailed discussion of the
Read Electronics portion of Figure 4-4 is contained in the following paragraphs.
4.6.3.1 Head Switch Circuitry
The Head
Switch circuitry disconnects the Read preamplifier signal inputs from the
read/write heads during a write/erase operation. This is done to prevent the large voltage
signal levels that are applied
to the head's read/write windings during a write operation
from entering the low level inputs of the
read preamplifier. Thus, the Head Switch circuitry
prevents the amplifier from being driven into saturation during a write operation.
4.6.3.2 Read Preamplifier
The Read Preamplifier is a single integrated circuit consisting of a wide band, linear
differential amplifier stage.
Read signals from the read/write heads are typically
quasi-sinusoidal with typical amplitudes of approximately 1 mv to 5
mv. The nominal
voltage gain of this amplifier is
50 in 100 tpi models and 150 in 200 tpi models; the read
signal output has an amplitude of approximately 200 to 400 mv peak-to-peak. The amplifier
gain is determined by a resistor of appropriate size across the gain-adjust terminals.
6300