5.5 LOGIC PCBA
The following paragraphs describe the Logic PCBA installed in 03000 Series Disk Drives.
Refer to Schematic No.1
02830 and Assembly No.1 02831.
The Logic PCBA is approximately 393.7 mm (15.5 inches) long by
273.1
mm (10.75 inches)
wide. Figure 5-6 illustrates the placement
of
each connector, test pOint, and adjustable
component on
this
PCBA. J104 and J105 connect via
3M
flat cable to the Servo PCBA;
J108, J109, J110, J111, and J112 are molex connectors which are
also connected
to
the
Servo PCBA. J103 mates
to
the Read/Write PCBA via
3M
flat cable.
J101
provides
connection between the
03000 and a controller or another
disk
drive. J102 provides
connection to the
PERTEC
1/0
Terminator PCBA or another
disk
drive. J114
(200
tpi
models only) transmits the three most significant
bits
from the current address counter
to
the Temperature Compensation PCBA.
The PCBA description is addressed
to
Schematic No. 102830 on a sheet-by-sheet basis
beginning with sheet
2.
5.5.1 SHEET 2 (SCHEMATIC NO. 102830)
Sheet
2 of the Logic PCBA schematic contains the Start I Stop Control logic portion
of
the
disk
drive function control logic. Refer to the functional description and simplified block
diagram contained in Paragraph 4.7 in conjunction with this discussion.
The crystal oscillator is comprised
of
transistor amplifiers 01 and
02
(zone
C14)
in
conjunction with the
10 Mt:lz crystal
Y1.
The crystal is connected
in
the feedback path of
the oscillator and is operated in a series resonant mode. The output signal
of
the oscillator
is developed across
R13
and is fed through inverter
U186
(which acts as a buffer) to the
clock countdown circuitry. The output
of
the oscillator can be monitored at TP13. The
clock countdown circuitry consists of cascaded 4-bit binary counters operating in a binary
countdown mode. The first counter of the countdown chain is a synchronous counter, the
remainder
are
ripple counters. The clock signals derived from the clock countdown chain
are
square-waves which are fed to various parts of the logic to provide the primary timing.
One of the clock signals is used in the spindle speed control logic to determine the speed
of the disk and functions
as
the primary
time
reference for the spindle speed control.
Another of the
clock signals, LC09F (U245 zone
B10)
is gated
by
the Sequence Timing
Pulse Flip-Flop (U345 zone
F5)
output pulse at AND gate U284-13 (zone 09) to produce the
gated
clock to the Purge Cycle Flip-Flop (U344 zone
G12)
and the Load Heads Flip-Flop
(U344
zone
G1
0). The frequency and the period
of
each one
of
the clock Signals is listed in
Table
5-1.
Referring to Table 5-1, it can
be
seen that each successive clock signal is
one-half the frequency and twice the period of the previous signal in the clock countdown.
NOTE
Generated clock signals are
listed
in Table 5-1 to
aid
in
troubleshooting;
all
of
these signals are
not
used in the
D3000.
The major states
of
the Start I Stop Control Logic
are
defined
by
the
Run
Flip-Flop (U364
zone H14), the End
Of Run Flip-Flop
(U364
zone H13), the Purge Cycle Flip-Flop
(U344
zone H12), the Load Heads Flip-Flop (U344 zone H10), the Sequence Control Flip-Flop
(U384
zone H9), the Brake Cycle Enable Flip-Flop (U384 zone H7), the Emergency Unload
Flip-Flop (U345 zone
E13),
and the Disk Rotation Detector Counter
(U283
zone 014).
5-19
6300
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