5.5.2 SHEET 3 (SCHEMATIC NO. 102830)
Sheet 3
of
the Logic PCBA schematic contains the remainder
of
the Disk Drive Function
Control Logic, i.e.,
all of the Disk Drive Function Control Logic which is
not
part
of
the
Start/Stop
Control Logic. The
Start/Stop
Control Logic description is contained in
Paragraph 5.5.1. Refer
to
the functional description and
simplified
block diagram
contained in Paragraph 4.7 in conjunction with the
following discussion.
Four of the
I/O
interface lines that control
disk
drive functions are routed
directly
to
the
Holding Register
(U308 zone H21) on the Logic PCBA. These lines are: Head Select
(IHSXR), Platter Select (IPSXR), Track Offset Plus
(ITOPR), and Track Offset Minus
(ITOMR). Note that Selected And Ready (NLSARG) is brought
to
the holding register
load-input. When NLSARG is low, the states on these
I/O
interface lines
will
be
copied
into the register. Thus, the state in the register
will
correspond
to
the state at the
1/
0
interface line and
will
change accordingly for any changes on the
I/O
interface line.
When the
disk
drive is de-selected, NLSARG will go high causing the holding register to
trap the last value
of
the inputs from the
I/O
interface. The register will then hold that state
until the next time the
disk
drive is selected. Note that Ready (NLRXXG) is used
as
the
clear input
to
the Holding Register U308. When high, NLRXXG causes the register
to
be
cleared
to
the all-zero's condition on each of
its
outputs. This condition
will
occur at any
time
the machine is in the Not-Ready condition. In other words, the pre-determined states
of logic zero on each
of
the output lines from the Holding Register, determine specific
states for the
Upper Head Select (NLUSHG), Upper Platter Select (NLUPSG), Track Offset
Plus (NLTOPG), and Track Offset Minus (NLTOMG) lines on the Logic PCBA.
Upper Head Select
(NLUHSG) is routed directly
to
the Read/Write PCBA, and the
Temperature Compensation PCBA, for head selection according
to
the state in the
Holding Register. Upper-Platter Select
(LUPSG), and its complement (NLUPSG), are
connected to various circuits on the Logic PCBA. These circuits are: the Write Protect
Logic for determining which Protect switches
will
be sampled, and the Multiplexer Control
Logic for determining which platter information
will
be
multiplexed
to
the 110 interface
output lines.
In
addition, NLUPSG is routed
to
the Read/Write PCBA
for
selecting a
specific storage surface, and
to
the Temperature Compensation PCBA,
to
enable the Head
Compensation Select circuitry.
NAND gates
U328
(zone
G19)
combine the Track Offset Signals from the Holding Register
with NLBTFF from the Position Control Logic. The results are that the Track Offset signals
will not
be
asserted
to
the Read/Write PCBA and the Servo PCBA during the
time
that the
positioner is busy. The outputs
of
these NAND gates are connected
to
the Servo PCBA and
the Read/Write PCBA via pins
22
and
23
of J103 and pins
26
and
25
of
J104.
NOTE
These signals
control
change
of
gain in the read
amplifier
on the Read/Write PCBA when
both
signals are asserted.
The
Signals are also fed to the Servo PCBA
and
are used to
assume operation
of
the Track Offset circuitry.
The Write Double Frequency Data Retransmitter
(U70
zone F21) functions
as
a line receiver
and
as
a line driver. The Write Data Signal (IWDSR) from the
I/O
interface is received by
U70
acting as a line receiver. IWDSR is the double frequency encoded
write
data from the
I/O
interface which must
be
transmitted to the Read/Write PCBA. Transmission of the
write data signal is also
accomplished by U70. Acting as a line driver, it drives the
NLWDFT signal
to
the Read/Write PCBA through J103 pin
27.
Thus, the Write data signal
is retransmitted
to
the Read/Write PCBA where it is used by the Read/Write electronics.
6300
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