6300
A stop sequence begins with zero-setting the
Run
Flip-Flop. This causes one-setting the
End
Of
Run
Flip-Flop which,
in
turn, causes the Sequence Control Flip-Flop to
be
pre-set
in
the event that it has not yet
been
one-set. To complete the stop sequence, the Brake
Cycle Enable Flip-Flop is one-set at the same time that the Sequence Control Flip-Flop is
zero-set. The stop sequence ends with zero-setting the Brake Cycle Enable Flip-Flop. The
End
Of
Run
Flip-Flop is used to detect the high-to-Iow transition of the
Run
Flip-Flop
when the
Run
Flip-Flop is zero-set. The End Of
Run
Flip-Flop, therefore, acts
as
an
edge
detector which is used
to
force a pre-set condition
to
the Sequence Control Flip-Flop. This
guarantees correct entry into the stop sequence.
The
Brake Cycle Enable Flip-Flop is then
one-set
to
define that portion of time when braking current is supplied to the disk motor
to
stop the disk.
The Emergency Unload
Flip-Flop
(U345
zone
E13)
defines the condition which causes the
emergency unload relay
to
disconnect the positioner servo from the positioner call and
connect the positioner coil
to
the emergency unload network. This is done when executing
an
emergency unload, or for preventing the connection
of
the positioner coil to the servo
electroniCS, prior
to
the
time
when the disk drive logic is capable
of
detecting certain
positioner electronic faults.
The Emergency Unload Logic is comprised of three basic parts:
U266
(zone 016) which
ANDs the Sequence Timing Pulse Flip-Flop with outputs from the Sequence Control Logic
and the specific signals to
be
tested for emergency condition indications during a start
sequence. The signals tested by
U266
logic are NLBPSL, NLPMXG, and LSOTF. The
ANDing of these
Signals generates, respectively, Brush Parking Error (NLBPEG), Head
Loading Error (NLHLEG), and Disk Starting Fault (NLDSFG).
Position Transducer Failure
(SPTFG) from the Servo PCBA is ORed with Write Emergency
Condition (RWECG) from the Read/Write PCBA at gate
U327
(zone
C17)
to produce
NLEOFG which is Emergency
Or Failure condition.
The Activate Emergency Unload
(IAEUR) line from the
I/O
interface is processed by a
minimum pulse width detector consisting of U147-8,
R10
and
C1
in
conjunction with
U286-6 (zone
B16)
to produce Emergency Unload Command (NLEUCG).
These signals plus Position Limit Error (NLPLEG), Disk
Speed Error (NLDSEG), and Seek
Time Error (NLSTEG) from other portions
of
the logic are combined in
OR
gate
U306
(zone
C15)
to produce Any Emergency (LAEXG). Assertion
of
LAEXG by one or more of the
emergency situations detected by the Emergency Unload Logic results in clearing the
Run
Flip-Flop and aborting the run condition. This pre-sets the Emergency Unload Flip-Flop
(U-345 zone
E13)
causing emergency retraction
of
the heads.
Lamp drivers U407-5, U386-5, and
U407-3
(zone
E4)
provide drive to the front panel
indicator lamps for the
SAFE,
RUN,
and
READY
lamps, respectively.
The Ready Logic (zone
E4)
combines the outputs of the Sequence Control Flip-Flop and
the Load Heads Flip-Flop with the
a output of the Emergency Unload Flip-Flop
to
produce
the
Ready
signal at the output of
U365
(zone
E5).
The Ready signal is combined with the
Selected signal at
U385
(zone
F4)
to
obtain the Selected And Ready condition for purposes
of gating the
line receivers and drivers for the
I/O
interface.
The
Selected And
Ready
(LSARG) Signal is processed by the trailing edge delay circuit
consisting of U444-6,
R16,
C4
(zone
C4)
in
conjunction with Schmitt trigger U405-6
to
produce the Delayed
Ready
Condition (LDRCG).
The
Delayed
Ready
Condition signal is
utilized in other parts of the logic for generating Malfunction Detected
(IMDXD) which is
an
I/O
interface signal.
5-24
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