, .
The
Run
Flip-Flop will
be
zero-set by any
Run
Switch Pulse
(LRSPG)
if
it
is already
one-set.
If the
Run
Flip-Flop is previously zero-set, then
LRSPG
will one-set the flip-flop
only if proper interlocking has occurred. Detection that the disk cartridge is correctly
inserted interlocks the
Run
Flip-Flop. Gate
U264-12
(zone
F15)
ORs
the Cartridge
Correctly Inserted
(LCCIG) signal with the Clear
Or
Unload (NLCOUG) Signal to clear the
Run
Flip-Flop
if
either or both of these signals
are
low.
Cartridge Correctly Inserted
(LCCIG) signal is developed from the states of the cartridge
inserted switches. The
Clear Or Unload (NLCOUG) signal is the
OR
condition
of
the Power
Clear Signal (SPCSA) and the output
of
the Emergency Unload Logic.
Determination of correct cartridge insertion is accomplished by two switches in top load
models
and
by a single switch in front load models. These switches connect to
J109
(zone
F18)
and
operate the Cartridge Inserted Latches. The output
of
the Cartridge Inserted
Latches is
ANCed by
U445-4
(zone
F17)
to generate the
LCCIG
signal.
The
cartridge
inserted latches are cross-coupled inverters in the same configuration
as
those used at the
input to the
Run/Stop Pulse Register. In front load models, where only one switch
Is
used,
one
of
the latches is held permanently in the correct state by a jumper
at
P109.
The
Run
condition is defined
as
any time that the disk Is rotating and a stop sequence
is not in progress, Le.,
Run
Flip-Flop one-set.
The
Run
Flip-Flop cannot
be
one-set
by a
Run
Switch Pulse signal unless the J input to the flip-flop is at a logic one level.
The
signal which enables the
Run
Flip-Flop J input is NLLCMG which is the result
of
combinational logic containing the remaining interlocking signals. These interlocking
signals
are:
Heads Retracted (SHRXG) which prevents entering a run condition unless the
heads
are
retracted; Not Disk Rotating (NLDRXG), from the Disk Rotation Detector
Counter, which prevents entering a run condition unless the disk is stationary; Not Brake
Cycle (NLBCFF), from the Brake Cycle Flip-Flop, which prevents entering a run condition
If a brake cycle is in progress; and, finally, the logic condition resulting from the
combination of the state
of
the Sequence Control Flip-Flop (LSCFF)
and
the
Run
Flip-Flop
(LRFFF) which is combined in
U385-3
(zone
E6)
to generate NLNRSG. This Signal is used
in
the interlocking control portion of the logic. The use of this arrangement prevents
re-entry into a run condition (Run Flip-Flop one-set) unless a correct stop sequence has
been
executed.
As
previously mentioned, there are two basic sequences executed by the Start/Stop
Control Logic; the start sequence,
and
the stop sequence.
A start sequence begins when the
Run
Flip-Flop is one-set
and
progresses through the
one-setting
of
the Purge Cycle Flip-Flop
(U344
zone
G12),
the one-setting
of
the Load
Heads Flip-Flop
(U344
zone
G10),
and
finally, the one-setting of the Sequence Control
Flip-Flop
(U384
zone G9). One-setting the
Run
Flip-Flop defines the run condition.
The
Purge Cycle Flip-Flop then defines that portion
of
the start sequence when the disk
speed
is increased to
10
percent above the nominal speed. This is done to increase the air flow
across the platter(s) prior to loading the heads.
The
Load Heads Flip-Flop is used
to
define
that state when the heads
are
loaded onto the disk(s). The Sequence Control Flip-Flop
defines the state which indicates the successful completion of a start sequence, or the
beginning of a stop sequence.
5-23
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