6300
SPCSA clears the Disk Rotation Detector Counter, pre-sets the Emergency Unload
Flip-Flop, clears the
End
Of
Run
Flip-Flop, clears the
Run/Stop
Pulse Register, the
Run
Flip-Flop, and the Sequence Timing Pulse Flip-Flop. The Power Clear Signal (SPCSA)
assures that the logic is properly initialized during power turn-on and that the logic
assumes the correct states in the event
of
power removal.
Commands which can cause the
Start/Stop
Control
to
execute either a start sequence
or
a
stop sequence are obtained from the
RUN
/ STOP control signal (CRSSS) connected to
J110, pins 1,
2,
and 3 (zone H18). A cross-coupled inverter latch
U447
is used
to
clean
up
the input signal and eliminate the problem
of
switch contact bounce. The output of
this
latch is ORed with the Start/ Stop Disk Drive (ISS
DR)
line from the
I/O
interface at U49.
The output of
U49,
pin
3,
is the input
to
the
Run
/ Stop Pulse Register (U347 zone G17). A
level change occurri
ng
either from
an
assertion
of
the Start / Stop Disk Drive line or from
actuation of the
RUN
/ STOP control is edge-detected by the Run / Stop Pulse Register. The
Run
/ Stop Pulse Register is a shift-register type
of
edge detector whose purpose is
to
produce a pulse having a period
of
one clock time upon detection of the leading edge
of
a
level change propagating through the register.
The one-clock period pulse
output
from U347 is the Run Switch Pulse (LRSPG) used for
clocking the Run
Flip-Flop (U364 zone H14).
In
addition, the
Run/Stop
Pulse Register
generates the
Start Drive Motor (NLSDMG) signal if, and only if, the Run Flip-Flop is
one-set
as
a result of the level change propagating through the Run / Stop Pulse Register.
This
will
be
the case when the Run Flip-Flop has been properly enabled and is one-set
to
commence a start sequence. The Start Drive
Motor
pulse initializes flip-flops in the
Spindle Speed Control logic on sheet 3 of the schematic.
The Delay Counter Decode logic (zone
E7)
is enabled
by
the outputs of the Sequence
Control Logic
as
well
as
the Sequence Control Flip-Flop. Delay Counter Decode decodes
specific values of delay by ANDing various bits from the Delay Counter according
to
the
states presented by the Sequence Control Logic and the Sequence Control Flip-Flop.
The Sequence Timing Pulse
Flip-Flop (U345 zone
E5)
is used
to
generate a pulse with a
period of one
clock interval when a high level is applied
to
the J input from the Delay
Counter Decode logic.
The sequence
timing
pulse is used
to
define the
timing
of
events during the start sequence
and the stop sequence.
It also tests the states of certain signals during the start sequence
for the purposes
of
determining
if
an
emergency condition exists.
The timing
of
two
of
the flip-flops is accomplished by using the sequence
timing
pulse
to
gate the clock to the Load Heads Flip-Flop and the Purge Cycle Flip-Flop. This is done
to
ensure clocking these fl ip-flops only at the end
of
specific delay intervals.
The Disk Rotation Detector Counter is used to detect disk rotation
tor
purposes
of
interlocking and
to
determine the duration of the brake cycle. Additionally, the Disk
Rotation Detector Counter provides a time delay at the end
of
the power clear condition.
The Sequence Control Logic (zone
E12)
is employed to decode the states of the Purge
Cycle Flip-Flop and the Load Heads Flip-Flop. This provides signals for steering the start
sequence and for initializing the position
monitor
circuit
in
the Position Control Logic.
The signal outputs from the Sequence Control Logic are
also used to enable the tests in
the Emergency
Unload Logic.
5-22
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