response while diodes
CR11
and
CR12
provide clipping action which allows the stage
to
operate over a large dynamic range.
C24
is used for stabilization and
CR69
prevents
latch-up.
For
100
tpi operation, the stage gain is designed to
be
approximately 9 at all-zeros
frequency at
1500
rpm, and
18
at all-ones frequency at
1500
rpm. For higher speed versions
of
100
tpi and for all
200
tpi operation, the gain is appropriately scaled.
The
system is
designed so that the minimum
all-ones frequency gain to the
peak
detector output is
1800
under normal conditions at
1500
rpm. Thus, for a
head
output
of
0.5
mv
peak-to-peak at the
all-ones frequency, the peak detector output is approximately 1.2v peak-to-peak.
The
output
of
the
peak
detector is
fed
to
U30
which provides a pulse output for
each
zero
crossing of the input signal. The width of the output pulse is proportional to
R157, R156,
and
C74,
R157
is employed
to
adjust the output pulse width to
40
to
45
nanoseconds.
5.4.8 DATA
DECODER
CIRCUITRY
The
Data Decoder circuitry acts upon the pulse former output to generate separated data
and
clock Signals. A functional discussion of this circuit is contained in Paragraph 4.6.3.7.
The
RPN
waveform consists
of
clock pulses which occur every
640
nanoseconds
(1500
rpm
and
2200
bpi) interspersed with a pulse
for
every one bit recovered.
The
RPN
waveform consists
of
clock pulses which occur every
640
nanoseconds
(1500
rpm
and
2200
bpi) interspersed with a pulse for every one bit recovered.
RPN
is gated through
U27-C
and
its leading edge is used to clock the appropriate one-shot
to set the ones window.
If the preceding clock period
had
a one interspersed, then the
short one-shot (U7-B) is used
to
form the ones window via U27-B.
If
the preceding clock
period did not contain a one, then the long one-shot (U7-A) is used to
torrn the ones
window via U27-B. U28-8 inverts the ones window to form the zeros or clock window. This
signal is applied
to
U27-C
and gates
RPN
through
R113
and
R115.
This is used to set the
period for the short
and
long one-shots.
If a
RPN
(data) occurs during the time that the ones window is high, it will
be
gated
through U27-A. This pulse sets U8-A which results in the short one-shot determining the
next one-shot period.
The
output of U27-A and
U27-C
are
fed back to the inputs
of
U27-8
and
U28-8,
respectively,
and
act
as
pulse stretchers.
The
outputs are also applied to U29-A and U29-8
where the decoding pulse is lengthened prior to sending down interface lines.
The
output
of U29-A is lengthened by
R153
but is also proportional to
R152
and
C7S.
The
output
of
U29-B
is lengthened by
R155
but is also proportional
to
R154
and
C77.
5.4.9 EMERGENCY CONDITION
DETECTION
Two conditions
are
detected by the Emergency Condition Detector circuitry
and
cause the
Write Emergency Condition
(RWECG)
Signal
to
go high.
The
NRWECG
signal is
fed
to the
Logic
PCBA
via
J305
pin
30
(zone
CS)
where it is used to initiate
an
emergency unload
sequence.
The
emergency unload sequence causes the unit to go Not Ready, thereby
turning
off
write current in less than 1
~sec.
The emergency unload sequence also causes
the emergency unload relay to operate, thereby interrupting the
S10SS
supply.
Interruption of this supply precludes any write current flowing
In
the heads.
One
emergency condition detected is the condition when more than one
head
is selected
while the disk drive is in a Write mode of operation.
When
a
head
is selected in the write
5-17
8300
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