6300
condition (e.g., the
head
connected to J300) the appropriate center tap is pulled to
approximately
10v
for tracks 0 through 127 and
7v
for tracks 128 through
202
(Paragraph
5.4.1
).
This voltage is clipped by
CR31
(zone
E14)
to
+0.7v
and fed via
R71
and diode
CR32
to the
inverting input
of
the type
741
operational amplifier
U4
(zone 011) which is used
as
a
comparator. A precision current drain for this circuit is established via
R75
to
-10"
The
non-inverting input of
U4
is
set at a nominal voltage
of
-4.5v
such that when one
head
is
selected the inverting input is more negative than
-4.5v
and the output of
U4
is high.
When
two heads
are
selected (e.g., the heads connected
to
J300 and J301) additional
current is
fed
via
R74
and
CR37
to the inverting input
of
U4
raising this point above
-4.5v
and
causing the output
of
U4
to switch to a negative state. This output is fed via
R134
and
CR53
to one input
of
the low active
OR
gate U26-A (zone 815) causing
RWECG
to go high
at
J305
pin
30
(zone
C6).
R138
and
CR58
prevent the input
to
U26-A from going more
negative than
-0.7v.
The
second emergency condition detected by this circuitry Is when write current is
on
during a
Read
operation. It is important to note that during a
Read
operation no write
current or erase current should flow.
Write
and
erase current must flow through
Rea
(zone 015) and the emitter base diode
of
019. If a total current in excess of approximately 0.7
rna
flows, then the voltage across
R63
(1
K ohm) will exceed 0.7v causing 019 to turn on. 019 conducting causes the input to
inverter
U26-C
(zone
A15)
to go low which, in turn, enables one input
of
NAND gate U26-8.
Recall that during a
Read
Mode, the Write Mode (NLWMXG) and Erase Current Enable
(NLECEG) Signals are high, thus the output
of
U22-C
(zone 817) is low.
In
the
Read
Mode the outputs
of
Inverter U22-C and non-Inverting driver
U25
are both high,
enabling the other two inputs of NAND gate U26-8. Thus, the output of
OR
gate U26-A
goes high and the
RWECG
waveform goes high at
J305
pin
30
(zone C6). Resistor
R143
and
capaCitor
C63
are used to provide masking delays to avoid false indications during
Read/Write switching.
During a Write operation, transistor
019
is on but one
or
both
of
the NLECEG and
NLWMXG waveforms are
low. Therefore, the output
of
UJ22-C
is
high, inhibiting gate
U26-8 and hence preventing
RWECG
from going high.
5-18
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