During a stop sequence, NLDMEG is high. When NL8CEG is also high (Le., brake cycle is
not enabled), the output at U19-A pin 3 (zone
E4)
is low and the signal at
TP22
is high all
the time,
and
the triac is turned off. Hence, the power to the motor is cut
off
and the motor
speed coasts down. When a brake cycle is enabled, NL8CEG is low, the signal at U19-A
pin 3 is high. Also, the signal at
TP28
(zone
C4)
is high all the time; hence signals at
TP23
and
U19-C
pin 8 (zone
C3)
are
60
Hz square
wave
digital output. Consequently, the
frequency of the reference sawtooth waveform at
TP27
is
60
Hz.
The
low state of NLBCEG
also makes U26-8 pin 5 at ground potential. Since NLlMS1 is high, the voltage at
TP24
is
approximately
2v
and U25-A pin 2 is approximately 0.7v. Thus the output at
TP22
is a
60
Hz
pulse train.
Since the frequency of the trigger pulses at
TP22
is
60
Hz
as
opposed to
120
Hz, the triac fires during only one-half of each cycle. The width of the pulse at
TP22
controls the firing angle
on
the
ac
waveform, therefore braking power applied during each
half cycle.
5.3.4
CARTRIDGE LOCK SOLENOID
DRIVER
The Cartridge Lock Solenoid Driver circuit is shown on Schematic No. 102810, sheet 2
(zone
B6).
This circuit consists of a transistor switch connected
in
series with lock
solenoids across +
5v
and -
20v.
J207 (zone 83) connects the coil of the lock solenoids to
the
Servo PC8A circuitry.
The Lock Cartridge Mechanism signal (LLCMG)
low at J202 pin
33
causes
043
and 042 to
turn on. This action applies approximately
24v
across the solenoid coil which energizes
the solenoids,
pulling the plungers into the coil. When LLCMG is high,
043
and
042
are
turned off, and the solenoid is de-energized, releasing the plungers.
5.3.5
POWER
CLEAR CONTROL CIRCUIT
The
Power Clear Control circuit is shown
on
Schematic No. 102810, sheet 2 (zone F4). This
circuit detects fault conditions in the
+
5v,
+
20v,
and
-20v
dc supplies
and
provides the
Power
Clear signal (SPCSA) to the Logic PCBA. J202 pin
30
(zone 88) connects the Plus 5
Volts signal (LP5VA) to the Power Clear Circuit at
TP26.
J202
pin
31
(zone
E3)
supplies the
Power
Clear signal (SPCSA) to the Logic PC8A.
Figure
5-4
illustrates the waveforms associated with fault detection
on
the +
5v
line.
The
Signals at various nodes in the circuit
have
been
drawn
on
the functional timing diagram
for explanation purposes and should
be
referred to
in
conjunction with Schematic 102810,
sheet
2.
LP5VA high (plot
1)
charges capacitor
C28
(zone 04) through
R181.
Zener diode
VR18
clamps and maintains the base of 038 to + 2.7v nominal (plot 2). Capacitor
C27
(zone 05)
is charged to approximately
+ 2.1v nominal through diode
CR49
and resistor network
R179
and
R195.
The charging time constant of
C27,
R179
and
R195
is much longer than that of
C28
and
R181.
Consequently, the base of
037
comes to the + 2.7v level with a slow rise
time (plot 3). When the base
of
037 is + 2.7v nominal, transistor 037 turns on and lowers
the voltage
on
the base
of
036 to less thatn +
5v,
turning
on
036.
The
collector
of
036 will
be
at approximately + 4.8v nominal. Resistor
R188
provides positive feedback to the base
of
037, hence, a clean, fast edge of the signal is obtained at the point
of
transition (plot
4)
and at
J202
pin
31
(SPCSA) (plot 5).
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