The Speed High
Limit
Flip-Flop, the Disk Speed·Low
Limit
Flip-Flop, and the Speed Low
Limit Flip-Flop are referred
to
as the speed value flip-flops. The specific values stored in
these
flip-flops
is the result
of
the previous speed count. After the values stored in the
speed
value
flip-flops
are
transferred to the speed status flip-flops (consisting
of
Increase
Motor Speed Flip-Flop and the Speed Out Of Tolerance Flip-Flop) by the Transfer Speed
Count
(L
TSCG) pulse, then, one-clock
time
later the speed control logic is reset by
NLSCRG which is a one-clock period low active pulse. This resets the Disk Speed Low
Flip-Flop, the Speed Low
Limit
Flip-Flop, and pre-sets the Speed High
Limit
Flip-Flop
to
establish the initial conditions at the speed value flip-flops for the next count. Also, the
Speed Control Counter is loaded with a pre-determined number from
the
Disk Speed Count
Programming array plug-in J122. This determines the
disk
speed count programming
according to the
state
of
the Purge Cycle Flip-Flop.
The speed control counter, U202,
U221
, and
U241
(zone F6,
7,
8), then counts from the
value loaded until the next Transfer
Speed Count pulse occurs. The rate
of
counting is
determined by the specific clock signals selected by the
Speed Control Programming array
plug-in J121.
If a count condition occurs in the Speed Control Counter which satisfies the
decode
of
either U223-8
or
U223-11,
or
U241
, pin 11, then that value will be stored in the
respective speed value
flip-flop. At the time
of
the next Transfer Speed Count pulse, the
value decoded and stored in the speed-value
flip-flop
will
then be transferred
to
the speed
status
flip-flops. Note that
two
different values may be loaded into the Speed Control
Counter at the time
of
a Speed Count Reset pulse. One is the normal running speed which
will occur when the Purge Cycle Flip-Flop is zero-set, and the other value is a
10 percent
overs
peed
which
will
be loaded when the Purge Cycle Flip-Flop is one-set.
The state
of
the Speed Out Of Tolerance Flip-Flop (U243 zone F3) is directly tested during
a start sequence to determine
if
there is a gross speed error prior to loading the heads.
Once the machine has reached the ready condition,
an
occurrence
of
a logic one at the
Speed Out Of Tolerance Flip-Flop
output
(LSOTF)
will
be gated by U343-6 with the Ready
signal producing the Disk
Speed Error (NLDSEG) signal. Disk Speed Error can therefore
occur only during the
time
that the
disk
drive is Ready.
The state
of
the Increase
Motor
Speed Flip-Flop at the end
of
each speed count interval
will indicate a basic binary error signal derived from the comparison of the
time
reference
to the actual speed. This
flip-flop
will be pre-set by the Start Drive Motor (NLSDMG) pulse
as
a means
of
initializing the speed status during a start sequence. Note that the result
of
the time-speed comparison is a single binary
digit
that can have only two possible states;
one
or
zero, indicating that the speed is either too fast or
too
slow. If it is
too
slow, the
Increase Motor Speed Flip-Flop
will
be in the one-set condition indicating that the motor
speed should
be
increased. Conversely,
if
the speed is
too
fast, the Increase Motor Speed
Flip-Flop will
be
zero-set, indicating that
it
is unnecessary for the
motor
speed to be
increased and
allowing the
motor
to coast down through the desired speed value.
5.5.3
SHEET 4 (SCHEMATIC NO. 102830)
Sheet
4 of the Logic PCBA schematic contains the Position Control Logic. Refer
to
the
functional description and simplified block diagram contained in Paragraph 4.7 in
conjunction with
this
discussion.
The
overall purpose
of
the Position Control Logic is to accept cylinder addresses from the
110
interface and control the positioning and holding
of
the positioner at those addresses.
The subsidiary function of this logic is to execute Restore operations and to
control
loading and unloading
of
the heads. The actual control functions within
this
logic are
performed by the Load Address Logic and Busy Logic, the Mode Control Logic, and
Operation
Control Logic.
5-29
I!3OD
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