1!300
one signal or the low active Selected signal (NLSXXG) depending on whether the machine
is a single platter or a dual platter drive, respectively. This selection is accomplished by
the sectoring selection programming array that is plugged into J125.
The Termination Voltage Power Supply is shown in
zorie
B11
of
the schematic. This is a
nominal 3.5v source which is provided
to
the interface
for
those models requiring
compatibility with
05000 termination voltage. This supply is derived by using diodes
CR1
and
CR2
in conjunction with
R25
to
provide a voltage drop from the internal +
5v
supply for
supplying termination voltage to connector
J102. Likewise,
CR3
and CR4, in conjunction
with
R26,
provides a reduced voltage from the +
5v
supply at J101. For those versions
of
the Logic PCBA that do not use the
iermination
Voltage Power Supply, pins
A45
and 845
on
J1
02,
are
wired to like pins on
J101
by jumper W3. This provides feed-through
of
the
termination voltage when this voltage is supplied by the controller.
In that case, CR1, CR2,
R25,
CR3,
CR4, and
R26
are omitted.
The Special Signal Driver (U65 zone
C12)
is a I ine-driver reserved
for
driving special
interface signals in those machines having that option (see Paragraph 3.17.13).
The Chassis Ground Connection is shown in zone
88
of
the schematic. For disk drives
having ordinary grounding,
W21
connects the
I/O
ground directly to the chassis. For
machines requiring ground isolation,
W21
is omitted and the
I/O
ground is connected to
the chassis ground through a complex impedence consisting
of
R72
and
C78.
The remainder
of
sheet 3
of
the schematic pertains to the speed control electronics. The
purpose of
this
circuitry is to compare the
time
of occurrence
of
the positive transition
of
the LPLFF
flip-flop
square-wave with the time reference obtained from the crystal
oscillator countdown (refer
to
Paragraph 5.5.1). The result
of
the comparison is two
Signals, one indicating the instantaneous speed error (NLIMSI) and,
if
appropriate,
another signal which
will indicate a gross malfunction
of
the speed control (LSOTF).
When the Drive-Motor Enable (LDMEG) signal is high and the drive
motor
is enabled to
operate, the Speed Sequence Register
U244
(zone C8), the Increase
Motor
Speed Flip-Flop
(U243 zone G4) and the speed out-of-tolerance Flip-Flop (U243 zone
F3)
are released to
operate. The
Speed Sequence Register, in conjunction with gates U224-10, U263-1,
U223-3, and U224-8 function as
an
edge detector. They also establish the sequencing of
the events in determining the disk speed. For each low
to
high transition
of
the Phase Lock
Flip-Flop signal (LPLFF) a one-clock-time pulse, Transfer
Speed Count (LTSCG), is
generated. One-clock-time thereafter
Speed Count Reset (NLSCRG) is generated to reset
the speed counting logic. The clock frequency utilized by the
Speed Sequence Register is
the same clock frequency counted by the
Speed Control Counter and is determined by the
particular programming array plugged into
J121
(zone F10), the Speed Control
Programming array. This selects one
of
three possible clock signals from the clock
countdown.
At the time the Transfer Speed Count (LTSCG) pulse
is generated, the states held in the
Speed High
Limit
Flip-Flop (U142 zone H5), the Disk Speed Low Flip-Flop (U242) and
Speed Low
Limit
Flip-Flop (U242) is transferred into the Increase Motor Speed Flip-Flop
(U243
zone
F3)
and the Speed Out Of Tolerance Flip-Flop (U243 zone F3). Specifically. the
state of the Disk Speed Low
Flip-Flop is transferred to the Increase Motor Speed
Flip-Flop. Either a one-set condition
of
the Speed High
Limit
Flip-Flop, or a one-set
condition of the Low
Limit
Flip-Flop is transferred to the Speed Out Of Tolerance Flip-Flop
if either of those flip-flops were one-set. This would
be
the case only
if
a gross speed error
is being detected.
5-28
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