The Write Protect Logic performs several functions on the Logic PCBA; one
of
these is
to
.
provide front panel indication via the Protect Lamp indicators as
to
the state
of
the Protect
Switches. The Write Protect switches connect
to
J108 and their states are sampled by the
Protect
Switch Latches
(U44S
zone
D1S)
and the Protect Lamp Drivers (U424 zone C13).
Drive is provided
to
the front panel Protect Lamp indicators according to the states
of
the
respective Protect
Switch Latches. There is one switch latch for each platter. For
single-disk machines with only one Write Protect switch the other switch input at
J108 is
permanently wired by a jumper in
P108
to disable the lower platter latch. Likewise,
for
those machines
not
fitted with Write Protect switches, jumpers in
P108
will
permanently
disable both Write Protect
Switch Latches. The state
of
the Protect Switch Latches is
decoded according to the specific platter selected by the interface. This is accomplished
by
U40S-S
(zone 014). LUPSG and NLUPSG are inputs to
this
AND/OR invert gate and
determine the specific Protect
Switch Latch which is sampled and fed
to
the File Protect
Mode Latch
U88
(zone 013).
The state
of
the respective Protect Switch Latch is fed
to
the File Protect Mode Latch if,
and only if, a Write
or
an
Erase operation is not in progress. This is the result of NAND
gates
U88-11
and U88-3 (zone 013). The purpose
of
this is
to
provide a signal that indicates
the specific platter that is protected from Write and
I or Erase operations. The state
of
the
File Protect Mode Latch is driven
onto
the File Protected (IFPXD) 1/0 interface line by the
File Protected
Status driver (U44 zone 012) according
to
the state
of
a File Protect Mode
Latch.
Also included
on
sheet 3
of
the Logic PCBA schematic are line drivers
for
several of the
interface output lines. The
Read
Signal Drivers
(US7
zone H12) take the
Read
Clock Signal
(NRRCSG)
and the
Read
Data Signal (NRRDSG) from the Read/Write PCBA via J103 and
drive these signals
onto
the interface lines
Read
Clock (IRCXD) and
Read
Data (IRDXD) via
J102.
The Malfunction Signal Driver
(US4
zone G12), and associated gate
U282
provide
an
indication when
an
internal malfunction is detected. The Malfunction Detected (IMDXD)
line
is pulsed when
an
internal malfunction is detected. This is accomplished by NANDing
the Delayed-Ready Condition (LDRCG) with the Emergency Unload Flip-Flop (LEUFF) at
NAND gate U282-8 and driving the resulting
Signal onto the Malfunction Detected (IMDXD)
lineatJ102.
.
Assuming that the disk drive is in the Ready condition
as
evidenced by the high level
of
LDRCG at pin 9
of
U282, any emergency will cause the Emergency Unload Flip-Flop to
one-set. One-setting the Emergency Unload
Flip-Flop causes the other input to
U282
to go
high. The high
level at pin 9 will persist for a short period
of
time
even
though the
disk
drive will go Not-Ready
as
soon
as
the Emergency Unload Flip-Flop is one-set. This is true
since the transition from Ready
to
Not-Ready will take a short period
of
time
to
propagate
through the Delayed Ready Condition circuit. Therefore,
for
that length
of
time, both
inputs
of
U282 will remain at the high logic level.
As
soon
as
the Ready to Not-Ready transition has propagated through the Delayed Ready
Condition circuit, pin 9 of
U282
will go low. This will terminate the Malfunction Detected
pulse that is applied to the interface output by
line driver
US4-5.
Double Track Drive (IDTDD) is indicated on certain models by driving the Selected
(NLSXXG)
signal onto this interface line. Illegal Cylinder Address (IICAD) is indicated at
the interface by driving that
line with the Illegal Address (NLlAXG) signal via
U3
(zone
E12).
NlIAXG
is generated in the Position Control Logic.
A dual platter drive is indicated at the interface by driving the Dual Platter Drive line with
the Dual Platter
Signal via
U45
(zone C12). Dual Platter Signal (NLDPSG) is made up in the
Sectoring Electronics (sheet 5
of
the Logic PCBA schematic) from either a steady logic
5-27
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