8300
The Unit Select Logic and the Busy Output Logic are shown in zone
17
through
21.
The
Unit
Select Logic is the decoding arrangement and the Busy Output Logic is
an
encoding
arrangement. Four separate Unit
Select lines
(IUS1
R,
IUS2R, IUS3R, and IUS4R) are
provided at the
I/O
interface and are presented
to
the circuit via J102. This allows selection
of
one
of
four disk drives on the common
I/O
bus. Internally, it is necessary for the drive
to
provide a signal which indicates that
it
is being selected
by
the
I/O
interface.
Since there are four separate and
distinct
select lines presented
to
the
disk
drive, they
must
be
decoded. The Unit Select lines
are
brought through
J101
, J102, and are decoded
according to the state
of
the Unit Number Selector Switch, which connects
to
J110, pins 5,
8,
9,
6,
and
7,
by
U89
and
U328-11
to
produce the Select Signal (LSXXG). When the Unit
Number
Select Switch on the front panel is set to one
of
the position numbers (one
through four), one and only one of the signals at U448-4,
U448-10, U448-8, and U448-6
will
be
high. This will result in the Select Signal (LSXXG) being generated only when there is
an
assertion on the specific Unit Select line that corresponds with the number
as
designated by the Unit Number Selector Switch on the operator's panel.
The busy output logic utilizes the same signals developed from the Unit Number Selector
switch to gate the Busy
Signal from the Position Control Logic onto the specific busy
seeking line that corresponds to the particular setting
of
the Unit Number Selector switch.
This is accomplished by U86-6, U86-5, U86-8, and
U86-11
(zone
B,
C-19). The common
inputs to these NAND gates are enabled by the AND condition
of
the Busy Signal (from the
Position
Control Logic) and the Ready signal. When the disk drive is Ready, NLRXXG
will
be
low, enabling U263-4 (zone
B19)
to provide a high output level whenever the Busy
Signal (NLBSXG) is low. This condition causes the Busy Signal
to
be transmitted on that
line selected by the setting
of
the Unit Number Selector switch.
U68
and
U69
(zone
B,
C-18) are line drivers for driving the Busy Seeking Signals onto the respective
I/O
lines.
The
Read
/Write Control Logic controls the Write, Erase and
Read
signals to the
Read/Write
PCBA. These signals depend upon the conditions
of
the input interface lines
and certain signals generated
on
the Logic PCBA. Additionally, the Read/Write Control
Logic generates NLWOEG which is supplied
to
the Write Protect Logic and the
Start/Stop
Control Logic.
The Write Enable (lWEXR) signal and the Erase
Enable (IEEXR) signal are received and
gated with Selected And Ready (NLSARG) by
U48-1
and U48-4 (zone G16). These gates
provide outputs only
if
the disk drive is selected and ready. The outputs
of
U48-1
and U48-4
are then gated
by
the AND condition of Position Mode (NLPMXG) and File Protect Mode
(LFPML). These signals
are
then routed to the Read/Write PCBA (via J103) as Write Mode
NLWMXG) and Erase
Current Enable (NLECEG) by two NAND gates, U87-3 and U87-4. The
Write Mode and Erase Current Enable signals to the Read/Write
PCBA will
be
asserted if,
and only if, the respective signal is received from the
I/O
interface, the
disk
drive is
selected and ready, the drive is not in a file-protect mode, and the positioner is in the
position mode.
If either Write Enable, Erase Enable, or both is present, the low active Write Or Erase
signal
(NLWOEG) will be generated at the output
of
U48
(zone G16). This signal is used in
the
Startl
Stop Control Logic to prevent clearing
of
the Load Heads Flip-Flop when either a
Write or
an
Erase operation is
in
progress. The signal is also used in the Write Protect
Logic to allow changing the state
of
the file protect mode latch only when a Write
and/or
Erase operation is not in progress. The
Read
Enable signal (IREXR) from the
I/O
interface
is gated only
by
Selected And Ready (LSARG) at NAND gate U87-8 (zone
F16)
before being
supplied
to
the
Read
IWrite
PCBA at
J1
03.
5-26
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