Cycle Enable signal is asserted, the Servo PCBA circuitry is caused to operate in a slightly
different mode wherein
full power is applied
to
the drive motor main winding but only for
one-half of a
line cycle. This develops a magnetic field in the drive motor which results in a
braking torque rather than in a running
or
starting torque. It is this torque which is used
to
slow the spindle to a stop.
4.7.4
POSITION CONTROL LOGIC
Figure
4-11
* is a functional block diagram
of
the Position Control logic and should be
referred
to
in conjunction with the following discussion.
The
major function of the Position Control logic is to accept address commands from the
110
interface and cause the positioner to move to the address demanded by the interface.
This involves generating suitable signals
to
control the mode
of
operation
of
the positioner
servo and to control the velocity that is used
by
the positioner servo. Additionally, certain
signals
are
generated which are supplied to the interface for purposes
of
indicating the
Position Control Logic status. Error checking
of
the Position Control Logic functions are
also accomplished by this logic.
The
major inputs from the
I/O
interface are the Cylinder Demand Address (ICDNR) lines,
the Cylinder Address Strobe (lCASR), and the Restore Initial Cylinder (IRICR) lines. Inputs
to the Position Control logic from the Servo PCBA are: Position Reference Clock
(SPRCG), Position Quadrature Clock (SPQCG), Position Transducer Index (SPTIG), Heads
Retracted (SHRXG). The signals from the
Servo PCBA are derived from the position
transducer. Additionally, the Load Head signal (LLHFF) is provided as
an
input to the
Position
Control logic from the Start I Stop logic and is used in the Mode Control logic.
Major output signals from the
Position Control logic to the Servo PCBA
are
the Address
Difference (NLADNG), Forward Direction (lFDX1),
Velocity Reference Enable (NlVREG),
Position Mode (lPMXG), Forward Slow Mode (NlFSM1), and Reverse Slow Mode
(NLRSM1). The major output signals which determine interface outputs are the
Illegal
Address (NlIAXG) and the Busy (NlBSXG) signal. The auxiliary output suppied
to
the
Read/Write
PCBA from the Position Control logic is Demand Address Most Significant
(lDAMG).
In
200
tpi models
an
auxiliary output consisting of the three most significant
bits from the current address counter are
supplied to the Temperature Compensation
PCBA.
A Cylinder Demand Address from the
I/O
interface specifies the nddress that is required
by
the controller. If the address is accepted by the Position ("ontrollogic, it is stored in the
Demand Address Register. Loading
of
this register is under control
of
the
load
Address
and
Illegal Address Control logic. The validity
of
a demand address on the
1/0
interface
lines is tested by the Valid Address Decoders, one decoder for 100 tpi addresses, and
another decoder for
200
tpi addresses. Only one decoder is connected, depending upon
the specific configuration
of
the machine.
The
inspection and test
of
the address is made only when accompanied
by
a Cylinder
Address
Strobe (ICASR) from the
I/O
interface.
In
addition, the state
of
Restore Initial
Cylinder (IRICR) line
is examined at the time
of
a Cylinder Address Strobe and the state
of
that line determines
if
the address is to
be
accepted
or
ignored, and
if
a restore operation
is to be performed.
When
the Restore Initial Cylinder line is asserted at the time
of
a
Cylinder Address
Strobe, the Demand Address lines are ignored and the Position Control
logic commences a Restore operation. A Restore operation initializes the Position Control
logic and returns the positioner to cylinder
000.
If
a Restore is not asserted at the time of a
*Foldout drawing,
see
end
of this section.
4-25
8300
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