The Mode Control portion
of
the Position Control Logie consists of the Position/Velocity
Mode Logic (zone
E5),
the Forward Slow Mode Flip-Flop (zone C4), and the
REVERSE
Slow Mode Flip-Flop (zone B4). The Position/Velocity Mode Logic determines when the
positioner servo should
be
operated in the Position Mode and when it should
be
operated
in
the Velocity Mode. This logic also supplies the Position Mode (LPMXG) signal and the
Velocity Reference Enable (NLVREG) signal to the
Servo PCBA.
The Forward
Slow Mode Flip-Flop
(U167
zone
C4)
determines the state of the Forward
Slow Mode (NLFSM1) signal, which is supplied to the Servo PCBA,
to
cause the
positioner servo
to
operate in the Forward Slow Velocity Mode. Likewise, the Reverse
Slow Mode Flip-Flop
(U206
zone
B4)
functions
to
store and provide a state which asserts
Reverse
Slow Mode (NLRSM1) to the positioner servo for operating the positioner
in
the
Reverse
Slow Velocity Mode. The Forward Slow Mode is used when loading heads
and
during the last portion
of
a restore operation. The Reverse Slow Mode is used when
unloading heads and during the first portion
of
a restore operation.
The
Forward Slow-Mode Flip-Flop (U167) is released for operation when the Load Heads
Flip-Flop (LLHFF) is one-set. Prior
to
loading, the heads will
be
retracted. This condition
is indicated by Heads Retracted (SHRXG) being high, which in conjunction with
one-setting the Load Heads
Flip-Flop, results in a high logic level from U187-4 (zone C5).
A high output at U187-4 causes the Forward
Slow Mode Flip-Flop
to
be
pre-set to
commence loading the heads.
Recall that the Forward
Slow Mode Flip-Flop (U167) is used also when performing a
Restore operation.
In
this
case, pre-setting the Forward Slow Mode Flip-Flop is controlled
by
the setting of the Restore Operation Flip-Flop
(U206
zone' A4). The Restore Operation
Flip-Flop
determines whether the address
as
asserted by the interface will
be
examined or
whether it
will
be
disregarded and a Restore operation performed.
The
Restore Operation Flip-Flop (U206) will
be
pre-set by the low active pulse from U49-6
(zone 86). This
pulse will occur if the Restore Initial Cylinder (lRICR) line is active at the
time that a
Cylinder Address Strobe (ICASR) is supplied from the
I/O
interface. At that
time, pins 4 and 5 of
U49
will
be
high, pre-setting the Restore Operation Flip-Flop. When
this
flip-flop is pre-set, U187-10 is enabled
to
pre-set the Forward Slow Mode Flip-Flop by
the negation of Position Transducer
Index (SPTIG) during the latter portion of a restore
operation.
The
Forward Slow Mode Flip-Flop is zero-set by the first high-to-Iow transition of Position
Quadrature
Clock (SPQCG) that occurs after the change of state of Position Transducer
Index (SPTIG) during loading
of
the heads. Since this occurrence must follow after the
change of state of Heads Retract (SHRXG), both
SHRXG and SPTIG are ANDed
by
U187-1
(zone
C5).
The
Reverse Slow Mode Flip-Flop
(U206
zone 84) is pre-set at the same time that the
Restore
Operation Flip-Flop (U206 zone
A4)
is pre-set when a Restore operation is
commanded. The Reverse
Slow Mode Flip-Flop can also
be
one-set when the Load Heads
Flip-Flop is zero-set. This results from (NLLHFF) being high, enabling the
J input of the
Reverse
Slow Mode Flip-Flop. The Reverse Slow Mode Flip-Flop is cleared when the
Forward
Slow Mode Flip-Flop is pre-set.
When either
of
the slow mode flip-flops are one-set, the demand address clear condition
will occur via U49-8 (zone C3). This
will clear the Demand Address Registers
(U301,
U321
,
U302
zone
E.
F,
G,
H-17). In addition, Demand Address Clear, in the form of a low active
signal (NLDACG),
will disable the Count Clock Detector Register
(U323
zone
C14)
by
clearing it to
an
all-zeros condition and will cause the Current Address Counter
(U322,
5-30
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