U381
,
U342
zone
E11
, 12, 13)
to
load all-ones. NLDACG also forces NLVREG
to
the high
logic level via U403-8 (zone
E4)
disabling the velocity reference, and forcing Not Position
Mode (NLPMXG).
In
this
manner, the logic is initialized and conditioned during the
time
the heads are being loaded
or
retracted,
or
during the execution
of
a Restore operation.
When a demand address clear condition does not exist (both the Forward
Slow Mode
Flip-Flop and the Reverse
Slow Mode Flip-Flop zero-set), the Count Clock Detector
Register (U323 zone C14), the Demand Address Registers (U301,
U321
, U302), and the
Current Address Counter
(U381
zone
E12)
will be released. The Velocity Reference Enable
and Position Mode signals will
be
under control
of
the other gates.
In
the
PositionlVelocity
Mode Logic, when Not Demand Address Clear (NLDACG) is high
(a
Demand Address Clear condition is not occurring), the Position Mode signal
will
be
asserted when the address difference is zero and Position Quadrature Clock is low. This
will
be
the case when the Current Address Counter contents agree with the Demand
Address Register contents and the positioner is
within
one-quarter track
of
the true-track
center line.
The purpose
of
the Load Address Logic is
to
generate a low-active pulse, Load Address
(NLLAXG) when a Cylinder Address Strobe
(ICASR) is received from the
110
interface and
the address on the Cylinder Address Lines is a valid address. Another function
of
this
circuitry is to generate a Busy signal
to
the
I/O
interface when a Strobe is received,
or
when the positioner is Busy Seeking. Another function
of
this
logic is
to
generate
an
illegal address indication
to
the
I/O
interface when the address on the interface lines is
invalid at the
time
that a strobe is received.
Cyl inder Address Strobe (ICASR) is received via J101, inverted, and shifted through the
Strobe
Sh
ift
Reg
ister
(U1
08
zone C12). When the level change first occurs at
bit
A of the
strobe
shift
register, the Hold Busy Time Flip-Flop (U128 zone
C9)
is caused
to
one-set,
which results in immediate assertion
of
the Busy Signal
to
the interface. This also releases
the previously cleared Hold Delay
Shift
Register (U146 zone C-9). The Hold Delay
Shift
Register, however, does not propagate logic ones because the Strobe
Shift
Register A
bit
is
still
in the logic one condition. The strobe trailing edge is edge-detected by the
combination
of
U127-4 and
U127-1
to
generate Address Pulse (LAPXG) (zone D11). LAPXG
samples the state on the Restore
Initial Cylinder Line (IRICR) at U49-6 (zone
B6)
to
determine if the Restore Operation Flip-Flop and the Reverse Slow Mode Flip-Flop should
be
pre-set to commence a Restore operation.
The Address Pulse also enables the input (pin 1) of
U107
(zone
D11)
and.
if
the cylinder
demand address is
valid (as determined by the Valid Address Decoder). and
if
the
positioner is not seeking (as determined by the state
of
the Busy Time Flip-Flop). then the
Load Address Pulse (NLLAXG) will
be
generated. This pulse causes the Demand Address
Register
to
load the address that is present
on
the Cylinder Demand Address Lines.
NLLAXG also clears the
Illegal Address Flip-Flop (U167 zone
B7)
if
it was one-set from any
previous
illegal address condition. When Strobe Shift Register Bit A goes low, at the
time
of the trailing edge of the Strobe, this causes logic ones to propagate through the Hold
Delay Shift Register. This level change propagating through the register may result
in
zero
setting the Busy Time
Flip-Flop (U128 zone B11). This removes the Busy Signal from the
interface if the positioner has
not
gone busy. This would
be
the case if
an
illegal address
or
an
address that is the same as the current position has been received.
It is important to note that the Strobe Shift Register is able
to
accept Cylinder Address
Strobes from the
1/0
interface only when it is released for operation by a high-logic level
on
the Selected And Ready (LSARG) line. Note also that the Illegal Address Flip-Flop
5-31
6300
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