(U167
zone
C7)
is clocked by the high to low transition of the Strobe Shift Register, bit A.
If the J input
of
the flip-flop is a logic one at the time
of
that transition, then the Illegal
Address Flip-Flop will
be
one-set. This would be the case
if
the Busy Time Flip-Flop is
one-set, or if the
output
of
the Valid Address Decoder is at the low logic level, indicating
an
invalid address. Therefore, the Illegal Address Flip-Flop will indicate
an
illegal address
if the positioner is
already busy, or if the address is invalid at the time of a Cylinder
Address Strobe. Notice that the Illegal Address Flip-Flop can be cleared by either
unloading of the heads, when LLHFF goes
low,
or
by a valid address being accepted,
when NLLAXG is generated, or
by
one-setting the Restore Operation Flip-Flop when a
Restore operation is commenced.
The
Illegal Address (NLlAXG) signal from
U167
(zone
B7)
is supplied to the interface by a
line driver (on sheet 3 of the schematic) only
if
the Selected And Ready (LSARG) line is at a
logic one
level. Also, during the time that the Strobe Shift Register, bit
B,
is in the logic
one condition, the
illegal address signal to the interface is disabled by
U107-11
(zone C7).
If
an
address is loaded into the Demand Address Register which is different than the
address stored in the Current Address Counter, then
an
address difference will
be
produced. This difference results in the Position Mode (LPMXG) signal going low. This
will cause pre-setting
of
the Busy Time Flip-Flop which indicates that the positioner will
be
busy executing a seek. This signal is supplied to the
I/O
interface. Additionally, the
Settle-Time Delay Register
(U109
zone
A11)
is cleared in preparation for determining the
settling
time
at the end of the seek.
Notice that the Busy
Signal (NLBXG) to the
I/O
interface from the Hold Busy Time
Flip-Flop (U128 zone
C10)
and the Busy Time Flip-Flop (U128 zone
B11)
is enabled
only
when these
flip-flops
are released by a high logic level
of
the Ready Signal (LRXXG). As
the positioner completes the seek, the address difference
will reach zero and the
positioner
will
reach a position that is within a quarter-track
of
the true-track center line.
At this time, Position Mode will
be
asserted causing LPMXG (zone 03)
to
go to the high
logic level. Since LPMXG is applied to the SeUle-Time Delay Register, it will commence
propagating
logic-one's through the register. After the delay, determined by the register
propagation time, the End Busy (LEBXG) signal
will cause zero-setting
of
the Busy Time
Flip-Flop and the Restore Operation Flip-Flop. This terminates the Busy
Signal
to
the
interface and also terminates any Restore operation status in the Operation
Control
portion
of
the Position Control Logic.
The
Settle Time
Del~y
Register (U109 zone A11) is clocked by LC13F from the clock
countdown. Therefore, the
delay
time
established by the Settle-Time Delay Register is
determined by the clock frequency and the number
of
bits that must be propagated after
the
level change on Position Mode (LPMXG).
The validity
of
a demand address on the
110
interface lines is tested
by
the Valid Address
Decoders. There is one decoder for
100-track per inch addresses (zone
C16)
and another
decoder for
200-track per inch addresses (zone 016). Only one
of
the decoders is
connected depending upon the specific configuration
of
the machine.
The Valid Address Decoder is combinational logic configured
to
provide
an
output signal
that
will
be
high
if
the input Cylinder Demand Address is within the legal range of values,
and to provide a
low logic level output when the Cylinder Demand Address lines have
an
address outside
of
the legal range. The range
of
legal addresses for
203
cylinder models is
from
000
to and including
202.
The range
for
legal addresses
for
406
cylinder models is
from
000
to and including
405.
As previously described, the Demand Address Register (U301,
U321
,
U302
zone
E,
F,
G,
16)
will either hold the last value, load a new value if the NLLAXG pulse occurs,
or
will be
cleared and held if a Demand Address
Clear condition occurs. Therefore, the contents
of
the Demand Address Register will either
be
all zeros or the last Demand Address loaded.
The contents
of
the demand address register therefore specify the present cylinder
demanded.
5-32
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