The current position of the positioner is stored
in
the Current Address Counter
(U381
zone
E12).
The
Current Address Counter is
an
up/
down counter. The direction and amount of
the count is determined by the count control on the basis of the Position Reference
Clock
(SPRCG)
and the Position Quadrature Clock (SPQCG) signals from the Servo PCBA. These
digital signals are derived from the outputs
of
the position transducer. During loading of
the heads, the Current Address Counter is first loaded
to
a condition
of
all-ones and then
counted by one up-count clock to
an
all-zeros condition to initialize the Current Address
Counter at cylinder
000.
Each high-to-Iow transition
of
the Position Quadrature Clock (SPQCG) is detected by
the Count
Clock Detector Register
(U323
zone C13). A one-clock time pulse is generated
for each high-to-Iow transition
of
SPQCG, and
this
pulse, via U383-4, is used
to
strobe the
Up/Down
Count Logic (zone E13).
If
during the time
of
the count clock pulse, Position
Reference
Clock (SPRCG) is high, the Current Address Counter will
be
counted down. If,
however,
SPRCG
is low during the time
of
a count clock, the Current Address Counter
will
be
counted up. A
UP
count increases the value in the address counter indicating that the
positioner is moving toward the spindle, and a
DOWN
count clock decreases the value
stored in the Current Address Counter indicating that the positioner is moving away from
the spindle.
During a seek, the positioner servo is operated
as
a velocity type of servo. A particular
velocity
level is determined on the basis of the amount of difference between the current
address and the demand address. This difference is specified to the Velocity Function
Generator on the
Servo PCBA by the Address Difference Lines
(NLADOG
through NLAD7G
and including NLADEG) (zone
E,
F, G, H-6).
The
address difference, that is the difference between the Current Address Counter
contents and the Demand Address Register contents, is obtained by performing a
ones-compliment arithmetic subtraction
on
the binary values of those counter and register
contents. This subtraction process is performed
by
the Subtractor (zone
F,
G,
H-10) and
Complimentor (zone
F,
G,
H-8). The actual subtraction is mechanized using
an
integrated
circuit binary full-adder.
Since the arithmetic is ones-compliment arithmetic
an
end around carry is used. This carry
is under control
of
the Carry Control Logic (zone E9). The algebraic sign
of
the velocity is
determined on the basis
of
the binary value of the carry which specifies the binary state
that is
on
the Forward Direction Line (LFDX1).
The
end around carry circuit can
be
traced on the schematic starting at
U402
(zone
H10)
at
the
C4
output and preceding to
U361
(zone 09), pin 2 and 13, and from there through the
Carry
Control Flip-Flop
U341
, pin 15, and then to the input of
U382
(zone E10). Note that
the input
to
Carry Control Flip-Flop determines the state on the Forward Direction Line
(LFDX1
).
As shown on the schematic the integrated circuit binary full-adder is connected in a
ripple-carry fashion to close the remainder of the end around carry loop. Notice also that
the input to the least significant adder from the output of the
Carry Control Flip-Flop
(U341-1S)
also controls the complimentor.
The
complimentor circuit is required for the situation where negative arithmetic is being
performed. The complimentor provides conditional inversion of the outputs of the
subtractor according to the state of the carry into the subtractor. Note that the subtractor
uses the content of the Current Address Counter directly, whereas the contents
of
the
Demand Address Register
are
complimented or inverted
by
the inverters shown in zone F
and
G13.
5-33
8300
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