The pulse formers are essentially
shift
registers (U22, U2,
U23
and U43) connected as
delays and edge detectors. The
actual pulse forming is accomplished by NOR-gates,
US3
(zone
G,
H through
B).
The clock used
for
determining pulse
timing
and delay is
LC04F
obtained from the
clock
countdown in the
Start/Stop
Control Logic.
The
outputs
of
the Upper and Lower Sector Pulse Formers are multiplexed
onto
the single
Sector
Pulse line (ISPXER
US2-8
(zone G4). The pulse driven by U44-3 (zone
G4)
depends
upon the particular platter selected by the interface. Likewise, the
outputs
of
the Upper
and Lower Index Pulse Formers are multiplexed by the Index
Pulse Multiplexer
(US2-S)
and
fed to the single
Index Pulse line (IIPXD) according
to
the
particular platter selected by the
interface.
The Sector Pulse Multiplexer and the
Index Pulse
Multiplexer
are controlled by the
Multiplexer Control Logic (zone F9) which also
controls
the Sector Count Multiplexer
according
to
the states
of
the Platter Select Line (LUPSG) and the Selected And Ready
(NLSARG) line. NLSARG enables the Multiplexer
Control gates only when the
disk
drive is
selected and ready. Thus, the
output
of
the Multiplexer Control
Logic
is gated with
Selected And Ready signal.
The specific multiplexer enabled, either the upper multiplexer
or
the lower multiplexer, is
determined at the input
to
the Multiplexer Control Logic by the states on NLUPSG and
LUPSG. These signals are derived from the Platter
Select Line
input
to the Disk Drive
Function Control Logic, as shown in sheet 3
of
the schematic.
When the
disk
drive is not selected,
or
not ready, then both.LUMEG and LLMEG
will
be
low, disabling the multiplexers. When the
disk
drive is Selected And Ready, then either
Upper Multiplexer Enable (LUMEG) will be high or Lower Multiplexer Enable (LLMEG)
will
be
high, according
to
whether the upper or the lower platter is being selected by the Platter
Select Line. Thus, the action
of
the Multiplexer Control Logie is to determine which
of
the
pulse and sector count
outputs
will
be
enabled and supplied
to
the
I/O
interface, J102.
The pulses obtained from the Sectoring Selection Programming array at J125 are also
applied to the Sector Number Counters and the Count Control Logic
to
generate the sector
count. The Upper Sector Number Counter (zone
E7,
8)
and the Upper Count Control
Flip-Flop (zone
DB)
generate the upper sector number count.
U144
and
U143
are the Upper
Sector Number Counters, and the count is controlled by the Upper Count Control
Flip-Flop U83. The Lower Sector Number Counter (zone B7,
8)
and the Lower Count
Control Flip-Flop (zone B8) generate the sector number count
for
the lower platter.
U125
and
U124
are the Lower Sector Number Counters, and the count is controlled by the Lower
Count Control
Flip-Flop
UB3.
The contents
of
the particular sector number counter are multiplexed onto the Sector
Count Lines
(ISCOD
through
ISCSD)
through the Sector Count Multiplexer (zone A, B,
C,
D.
E-5)
according
to
the control signals generated by the Multiplexer Control Logie. U84,
U104. U105, and
U85
form the Sector Count Multiplexer. One
or
the other
of
the sector
number counter contents
will
be selected and supplied
to
the line drivers according
to
the
control signals from the Multiplexer Control Logic. For each sector count line, there is a
separate line driver. The specific sector number count, multiplexed
onto
the sector count
lines, is determined by which platter is selected by the Platter Select Line and
will
only be
presented
to
the
I/O
interface
if
the
disk
drive is Selected and Ready.
The mechanization
of
the Upper Sector Number Counter and Upper Count Control is
identical
to
that used with the Lower Sector Number Counter and Lower Count Control.
Therefore, only the Upper Sector Number Counter and Upper Count Control Flip-Flop
will
be
explained.
5-39
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