6300
The
output of the Sector PLL Countdown Counter is fed to the clock input of the Sector
Countdown Divider
Flip-Flop
U129
(zone B20).
The
Sector Countdown Divider Flip-Flop
converts the output
of
the Sector PLL Countdown Counter into a square
wave.
This square
wave
is the other input to the Phase Comparator and Filter.
The
phase comparator is
comprised of
U147
(zone A, B, C-19),
R46, R49,
R47,
and
R48.
The
output
of
the Phase Comparator is filtered and applied to the input of the
Sum-And-Difference
Amplifier,
U168
(zone B19).
The
filter is comprised of
R51,
R52, R53,
R58,
C16,
R54,
R55,
R56,
R59,
C17.
The
particular filter characteristics required
are
programmed
by
part of
J123
depending upon the disk speed utilized in the particular disk
drive.
R60,
R64,
R61, R62,
and
R63
determine the characteristics and gain of the
Sum-And-Difference
Amplifier,
U168.
C19
and
C20
decouple the power supply to
U168.
Adjustment of the PLL is accomplished by
R57
(zone A18). The combination of
R50,
CR5,
CR6,
R57,
C18,
R62,
and
R63
provide a bias to the Sum-And-Difference Amplifier
and
the
SectorVCO.
The
output
of
the Sum-And-Difference Amplifier,
U168,
pin
6,
is the control voltage to
control the frequency of the
Sector
VCO.
It is filtered by
R65
in conjunction with
C21.
This
control voltage causes the
Sector
VCO
frequency to become phase-locked to the
pulse-trained derived from the Phase Lock Ring.
The output of the
VCO,
which connects to
TP16
(zone 815), is the input
to
the Countdown
Counter and the
VCO
divider flip-flop.
The
Divider Flip-Flop divides the frequency of the
Sector
VCO
by
a factor of 2 for use
as
an
alternate input to the Countdown Counters
depending upon the desired number
of
sectors. Whether the output
of
the
VCO
Divider
Flip-Flop or the output of the
VCO
directly is applied to the Sector Countdown Counter is a
function of the particular programming array installed in J125.
The
Lower Sector Countdown Counter and the Lower Synchronizer will now
be
described.
Operation of the Upper Synchronizer and the Upper
Sector Countdown Counter is similar.
The
Lower Sector Countdown Counter consists
of
U121, U161,
and
U181
(ione 010, 11,
12). These are 4-bit binary synchronous counters that may
be
loaded with one of two
different values obtained from the Lower Electronic
Sector Programming array installed at
J127.
The
value loaded is determined by the Lower Synchronizer Register and associated
circuitry which generate the
I and
NI
signals applied to the Lower Electronic Sector
Programming array, pins 5 and
6,
respectively.
The
Lower Sector Countdown Counter is clocked
by
the signal obtained from the
Sectoring
Selection Programming array which will
be
either the output of the
VCO
Divider
Flip-Flop or the output of the Sector
VCO
directly.
When the Lower Sector Countdown Counter is counted from the value loaded until a
carry-out occurs at
U181
(zone 010), a pulse will
be
output at
U122,
pin
4.
This pulse train
output has a frequency which corresponds to the number
of
desired sectors. This pulse
train
will
be
synchronized with the index
by
the Lower Synchronizer Register (zone 013)
and
the associated synchronizing circuitry. That circuitry consists of
U182
(Lower
Synchronizer Register), U162-12, and
U122-1
which edge detects the pulse obtained for
the lower platter index
by
the Lower Time Demultiplexer which outputs from
U183,
pin
10
(zone 015).
5-42
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