6300
The
Velocity Function Generator is a digital-to-analog converter which has a single
polarity output.
The
address difference input is a digital signal that is the binary
representation of the difference between the demand address from the interface
and
the
current address defining the current positioner position. The output of the Velocity
Function Generator is
an
analog voltage representative of the address difference.
Therefore, the specific velocity requested is a function of the distance
to
be
traveled in
achieving the demand address.
The
address difference is specified
on
the Address Difference lines in binary form where
NLADOG
Is
the least significant bit and NLADEG is the most significant bit. The decimal
address difference number may
be
expressed as the sum of the active
bit
weights.
Each
address difference being assigned a specific bit weight. The bit weights
are
ascending
powers of two, where bit number
0 is decimal bit weight number 1; bit number 1
is
decimal
bit weight number
2;
bit number 2 is decimal bit weight number
4,
etc.,
to
the extension bit
number where the bit weight is
256.
The address difference
as
specified
on
the Address
Difference lines determines the magnitude
of
the velocity reference generated by the
Velocity Function Generator.
Referring to the
Servo Board Schematic No.
102810,
it
can
be
seen
that the Velocity
Function Generator portion
of
the velocity function decoder/encoder consists of
U12C,
U12B,U5B, U5A, U4C,U5C, U4B, U5D,U4D, U3D,U4A,U3C,
U4E,
U3B, U4F,U3A.
The
remainder of the Velocity Function Generator is the digital-to-analog conversion
arrangement consisting of a resistor network, a current-to-voltage converter,
and
diode
switches.
The
purpose
of
this arrangement is
to
take the digital signal encoded
by
the
velocity function decoder/encoder and convert it into a current
of
a specific value which is
then
applied to the current-ta-voltage converter. The summing junction of
U8
(located
on
the Servo PCBA) functions
as
a current-ta-voltage converter producing a voltage level
which is determined by the address difference value. The resistor network is
R1,
R2,
R7,
R8,
R10,
R11, R16, R17, R18, R19,
R20,
R21,
R24, R25.
The diode switches
are
CR1
through
CR12.
The current-to-voltage converter consists of
U8
in conjunction with 01.
Referring to Figure 4-2, the output magnitude of the
Velocity Function Generator is the
velocity reference which is utilized during seeks. This reference is determined
by
the
address difference value. The polarity of the velocity reference which determines the
direction of the velocity is controlled by the Polarity
Select Network. The Polarity Select
Network in turn is controlled by the Forward Direction (LFDX1) line from the Position
Control Logic.
The
Transistor Switch, which switches the velocity reference to the
Summing Amplifier, is controlled by the Velocity Reference Enable (NLVREG) line from
the Position
Control Logic. When the positioner is executing a high-speed seek
and
is not
operating
as
a position servo, the Velocity Reference Enable (NLVREG) line will
be
active,
thereby switching to the velocity reference from the Velocity Function Generator.
Other commands which may be applied to the input of the
Summing Amplifier
are
for
controlling the
pOSitioner in the Slow Velocity mode, i.e., during loading and unloading of
the heads.
The
Slow Velocity mode is also used when executing a Restore operation.
The
Slow Velocity mode is determined by a velocity reference in the Mode Control Circuits,
which
in
turn
are
controlled by two logic signals, Forward Slow Mode (NLFSM1)
and
Reverse
Slow Mode (NLRSM1).
The
two slow mode control signals,
NLFSM1
and
NLRSM1
, are developed by the Position
Control Logic
and
control transistor switches in the Mode Control Circuits which establish
the
Slow Mode velocity reference. Transistor switch
07,
in conjunction with
R44,
CR21
,
R45,
and
R46
on
the
Servo
PCBA,
are
used for switching
and
determining the
level
of the
Forward
Slow Mode velocity reference.
4-8
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