words, the actual phase angle during the power line cycle where power is applied to the
main winding
of
the drive motor is the result
of
the integral of the binary speed error. This
determination is made from the comparison
of
the actual speed sensed by the Magnetic
Transducer to the time reference derived from the Crystal
Oscillator.
Refer to Figure 4-10*, a functional block diagram of the Spindle Speed Control Logic, for
the following discussion.
Operation
of
the spindle speed control can best be understood
by
starting at the Spindle
and
going around the loop. The Magnetic Transducer senses the
notches in the
Phase Lock Ring
and
produces a signal which is then processed by the
Sector Electronics Logic (refer to Paragraph 4.7.5).
The results
of
the action taken
by
the Sector Electronics logic is the output
of
a flip-flop
called the Phase Lock Flip-Flop (LPLFF). This flip-flop functions as a frequency divider
on
the basic frequency derived from the Phase Lock Ring and converts the pulse as processed
by the sector electronics into a square
wave.
The Phase Lock Flip-Flop signal (LPLFF) is
fed into the
Speed Sequence Control
as
shown
in
the block diagram.
Clock signals derived from the Crystal
Oscillator and Clock Countdown (LC02F, LC03F,
LC04F)
are fed to the Speed Control Programming logic, then to the Speed Control
Counter.
The
time between the occurrences of low to high transitions of the Phase Lock
Flip-Flop signal is detected by the
Speed Sequence Control logic. Detection of this
transition causes the
Speed
Sequence Control to generate two pulses which are
synchronous with the clock signal specified by the
Speed Control Programming logic.
These pulses determine the sequence
of
the time comparison.
The desired value of disk speed is programmed
by
the Disk Speed Count Programming
array. The program value
fed
to the Speed Control Counter is determined by the array and
the state of the
Purge Cycle Flip-Flop (LPCFF), thereby providing a nominal speed for
normal operation and
an
over-speed value
for
use during the purge cycle. The programmed
value
of
the disk speed count is fed to the Speed Control Counter logic and the selected
clock signal from the
Speed
Control Programming logic is then counted by the Speed
Control Counter. The results
of
the count are stored in the Speed Value Flip-Flops and,
when appropriate, transferred to the
Speed Status Flip-Flops
as
determined by the Speed
Sequence
Control logic. The actual comparison of the spindle speed to the reference
signal occurs on the basis
of
the count totalized in the Speed Control Counter logic during
the time interval defined between transitions
of
the Phase Lock Flip-Flop.
There
are
two
outputs derived from the Speed Status Flip-Flops; the Increase Motor Speed
(NLlMS1)
signal and the Speed Out Of Tolerance (LSOTF) signal. The Speed Out Of
Tolerance signal indicates when the
disk
speed is detected as being out
of
tolerance by the
Speed Value Flip-Flops. This information is tested during the start sequence and is also
combined in a Gate with the
Ready
signal (LRXXG) to produce Disk Speed Error
(NLSDEG). The Increase Motor
Speed signal is fed to the Servo PCBA and is the basic
binary error signal derived from the comparison of the time reference to the actual speed.
The
Start Drive Motor pulse (NLSDMG) is used for intializing the speed status flip-flops
during a start sequence and the Drive Motor Enable (LDMEG) line is used for initializing
the
Speed Sequence Control and the Speed Status Flip-Flops.
It
can
be
seen
that the purpose of the circuitry
on
the Logic PCBA is to convert the analog
signal obtained from the Magnetic Transducer into a suitable digital square
wave,
then
compare the time
of
occurrence
of
the positive transitions
of
that square
wave
with a time
reference obtained from a Crystal
Oscillator. The result of that comparison is two Signals,
one indicating the instantaneous speed error signal and,
if
appropriate, to provide a signal
*Foldout drawing,
see
end of this section.
4-23
6300
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