Renesas RH850/F1Kx Series Hardware Design Guide

RH850/F1Kx, RH850/F1K Series Hardware Design Guide
R01AN3841ED0110 Rev. 1.10 Page 100 of 108
August 8, 2019
Note:
Design the circuit in the way that the FLMD1 pin must be at the low level during serial
programming. During programming (using the RFP), it outputs a low level on FPMD1 to place
the device in the serial programming mode.
If necessary, connect FPMD1 and FLMD1.
The flash programming signal connection of the E1/E2 interface is given in the table below:
Table 73: E1/E2 Flash programming signal connection
E1/E2 Interface Connector
E1/E2 Signal
Device Pin
1
-
-
2
GND
EVSS
3
-
-
4
FPMD0
FLMD0
5
FPDT
JP0_1
6
FPMD1
FLMD1
7
FPDR
JP0_0
8
TVDD
EVCC
9
-
-
10
-
-
11
-
-
12
GND
EVSS
13 RESET RESET
14
GND
EVSS

Renesas RH850/F1Kx Series Specifications

General

Brand	Renesas
Model	RH850/F1Kx Series
Category	Computer Hardware
Language	English