RH850/F1Kx, RH850/F1K Series Hardware Design Guide
R01AN3841ED0110 Rev. 1.10 Page 51 of 108
August 8, 2019
1.5.4 Power Supply Timing of RH850/F1K
The RH850/F1K has a recommended power supply timing.
The voltage slope of the different power supply pins is defined with min. 0.02V/ms and max. 500V/ms. Satisfy the spec
of voltage slope by using power IC with enable control or by using power IC which starts output over VPOC. The
following shows an example of configuration between RH850/F1K and PMIC.
Figure 17: Recommended REGVCC power configuration for RH850/F1K
The voltage range which has to be kept voltage slope is as follows. There is no voltage slope limitation at the case other
than below condition. For detail, see the following figure.
Figure 18: The voltage range which has to be kept voltage slope for RH850/F1K
Note: When the power source rises again, keep the spec of “REGVCC minimum width (t
w_POC
)“ that is specified in
the Section 40.8.2 Voltage Detector (POC, LVI, VLVI, CVM) Characteristics of the RH850/F1K Hardware
User’s Manual.
For details on the electrical characteristics, please refer to the Electrical Characteristics of the RH850/F1K Hardware
User’s Manual.
PMIC
+B
VINx
VOUT1
REGVCC
EVCC
RH8 50 /F1K
: Voltage range that tVS shall be kept
REGVCC/EVCC/
A0VREF/A1VREF
3.0V (VPOC (max))
0V
2.7V (VPOC (mi n))
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