RH850/F1Kx, RH850/F1K Series Hardware Design Guide
R01AN3841ED0110 Rev. 1.10 Page 73 of 108
August 8, 2019
4.3 General Purpose I/O
4.3.1 RESET State of General Purpose I/P
During RESET state, all general-purpose I/O pins are in input mode with high-Z behavior except the pins
JP0_4/ DCUTRST
and P8_6/ RESETOUT .
4.3.2 JP0_4/ DCUTRST
During power-on or when RESET
is at low level the pin JP0_4 should not be driven externally to high-level.
Therefore, JP0_4/
DCUTRST has to be connected in all device operation modes to EVSS via a resistor.
4.3.3 P8_6/ RESETOUT
When the RESETOUT
signal is selected for the P8_6 pin the output on the pin is at low level during a reset and after
release from the reset state depending on the option byte setting (OPBT0[9] register).
For further details, please refer to Sections 2A.11.1.1, P8_6:
RESETOUT , 2B.11.1.1, P8_6: RESETOUT and
2C.11.1.1 P8_6:
RESETOUT of the RH850/F1KH, RH850/F1KM Hardware User’s Manual.
For further details, please refer to the Section 2.11.1.1, P8_6:
RESETOUT of the RH850/F1K Hardware User’s
Manual.
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