RH850/F1Kx, RH850/F1K Series Hardware Design Guide
R01AN3841ED0110 Rev. 1.10 Page 4 of 108
August 8, 2019
Table of Figures
Figure 1: RH850/F1KM-S1 Power supply architecture ..................................................................................... 9
Figure 2: Recommended REGVCC power configuration for RH850/F1KM-S1 .............................................. 12
Figure 3: The voltage range which has to be kept voltage slope for RH850/F1KM-S1 .................................. 12
Figure 4: RH850/F1KM-S1 Power up/down timing ......................................................................................... 13
Figure 5: RH850/F1KM-S1 Power up/down timing ......................................................................................... 13
Figure 6: RH850/F1KM-S4 Power supply architecture ................................................................................... 16
Figure 7: Recommended REGVCC power configuration for RH850/F1KM-S4 .............................................. 27
Figure 8: The voltage range which has to be kept voltage slope for RH850/F1KM-S4 .................................. 27
Figure 9: RH850/F1KM-S4 Power up/down timing ......................................................................................... 28
Figure 10: RH850/F1KM-S4 Power up/down timing ....................................................................................... 28
Figure 11: RH850/F1KH-D8 Power supply architecture .................................................................................. 30
Figure 12: Recommended REG0VCC power configuration for RH850/F1KH-D8 .......................................... 41
Figure 13: The voltage range which has to be kept voltage slope for RH850/F1KH-D8 ................................ 41
Figure 14: RH850/F1KH-D8 Power up/down timing ........................................................................................ 42
Figure 15: RH850/F1KH-D8 Power up/down timing ........................................................................................ 43
Figure 16: RH850/F1K Power supply architecture .......................................................................................... 45
Figure 17: Recommended REGVCC power configuration for RH850/F1K ..................................................... 51
Figure 18: The voltage range which has to be kept voltage slope for RH850/F1K ......................................... 51
Figure 19: RH850/F1K Power up/down timing ................................................................................................ 52
Figure 20: RH850/F1K Power up/down timing ................................................................................................ 52
Figure 21: Principle capacitor placement at REGVCC for EMI ....................................................................... 53
Figure 22: Minimum external components of RH850/F1KM-S1 in normal operating mode ............................ 54
Figure 23: Minimum external components of RH850/F1KM-S4 in normal operating mode ............................ 58
Figure 24: Minimum external components of RH850/F1KH-D8 in normal operating mode ............................ 61
Figure 25: Minimum external components of RH850/F1K in normal operating mode .................................... 64
Figure 26: Recommended main oscillator circuit ............................................................................................ 67
Figure 27: Recommended sub oscillator circuit .............................................................................................. 68
Figure 28: Direct clock supply to X1 (MOSC) .................................................................................................. 70
Figure 29: Minimum RESET circuit ................................................................................................................. 71
Figure 30: External RESET timing ................................................................................................................... 72
Figure 31: Analog filter function ....................................................................................................................... 74
Figure 32: Mechanism of injection current....................................................................................................... 85
Figure 33: ADC conversion time ...................................................................................................................... 87
Figure 34: ADC equivalent input circuit ........................................................................................................... 88
Figure 35: ADC external circuit on analog input .............................................................................................. 89
Figure 36: Schematic for sampling error 1 formula ......................................................................................... 90
Figure 37: Schematic for sampling error 2 formula ......................................................................................... 91
Figure 38: LPD (1 pin) connection ................................................................................................................... 93